View MAX866009_4554141.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-0587; Rev 2; 8/09
KIT ATION EVALU ABLE AVAIL
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
General Description
The MAX8660/MAX8661 power management ICs (PMICs) power applications processors (APs) in smart cellular phones, PDAs, Internet appliances, and other portable devices. Four step-down DC-DC outputs, three linear regulators, and an 8th always-on LDO are integrated with powermanagement functions. Two dynamically controlled DCDC outputs power the processor core and internal memory. Two other DC-DC converters power I/O, memory, and other peripherals. Additional functions include on/off control for outputs, low-battery detection, reset output, and a 2-wire I2C serial interface. The MAX8661 functions the same as the MAX8660, except it lacks the REG1 step-down regulator and the REG7 linear regulator. All step-down DC-to-DC outputs use fast 2MHz PWM switching and tiny external components. They automatically switch from PWM to high-efficiency, light-load operation to reduce operating current and extend battery life. In addition, a forced-PWM option allows lownoise operation at all loads. Overvoltage lockout protects the device against inputs up to 7.5V.
Features
o Optimized for Marvell PXA3xx and PXA168 Applications Processors o Protected to 7.5V--Shutdown Above 6.3V o Four Synchronous Step-Down Converters REG1, REG2, REG3, REG4 o Four LDO Regulators REG5, REG6, REG7, REG8 o 2MHz Switching Allows Small Components o Low, 20A Deep-Sleep Current o Low-Battery Monitor and Reset Output
MAX8660/MAX8660A/MAX8660B/MAX8661
Ordering Information
PART PIN-PACKAGE OPTIONS V1: 3.3V, 3.0V, 2.85V V2: 3.3V, 2.5V, 1.8V V3: 1.4V (default) V4: 1.4V (default) V1: 3.3V, 3.0V, 2.85V V2: 3.3V, 2.5V, 1.8V V3: 1.4V (default) V4: 1.4V (default)
MAX8660ETL+
40 Thin QFN
Applications
PDAs, Palmtops, and Wireless Handhelds Smart Cell Phones Personal Media Players Portable GPS Navigation Digital Cameras
MAX8660ETL/V+
40 Thin QFN
Note: All devices are specified over the -40C to 85C operating temperature range. +Denotes lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Ordering Information continued at end of data sheet.
Pin Configuration
PG3 RAMP RSO PV3 EN5 LBR LX3 MR V3
Simplified Functional Diagram
MAIN BATTERY
TOP VIEW
30 29 28 27 26 25 24 23 22 21 EN34 31 EN2 32 SRAD 33 PG1 (GND) 34 LX1 (N.C.) 35 PV1 (PV) 36 EN1 (GND) 37 V1 (GND) 38 SET1 (GND) 39 V4 40 1 IN5 2 V5 3 PV4 4 LX4 5 PG4 6 SET2 7 V6 8 IN67 (IN6) 9 V7 (N.C.) 10 V2 EXPOSED PAD (EP) 20 V8 19 AGND 18 IN 17 IN8
LBF
IN MAX8660 LBR LBF
V1
VCC_IO: (PIN PROG) 3.3V/3.0V/2.85V AT 1.2A VCC_MEM: (PIN PROG) 1.8V/2.5V/3.3V AT 0.9A VCC_APPS: (I2C PROG) 0.725 TO 1.8V, DVM AT 1.6A VCC_SRAM: (I2C PROG) 0.725 TO 1.8V, DVM AT 0.4A VCC_MVT: (I2C PROG) 1.7V TO 2.0V AT 200mA VCC_CARD1: (I2C PROG) 1.8V TO 3.3V AT 500mA VCC_CARD2: (I2C PROG) 1.8V TO 3.3V AT 500mA VCC_BBATT: 3.3V ALWAYS ON AT 30mA
V2 V3 V4
MAX8660ETL+ MAX8660AETL+ MAX8660BETL+ MAX8661ETL+
16 PG2 15 LX2 14 PV2 13 LBO 12 SDA 11 SCL
nBATT_FAULT nRESET
LBO RSO MR V5 V6 V7 V8
I INTERFACE
2C
SCL SDA EN1,2,5 EN34
SYS_EN PWR_EN
THIN QFN 5mm x 5mm x 0.8mm
( ) ARE FOR THE MAX8661
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Table of Contents
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Simplified Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Maxim vs. Marvell PXA3xx Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Step-Down DC-DC Converters (REG1-REG4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 REG1 (VCC_IO) Step-Down DC-DC Converter (MAX8660 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 REG2 (VCC_IO, VCC_MEM) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 REG3 (VCC_APPS) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 REG4 (VCC_SRAM) Step-Down DC-DC Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 REG1-REG4 Step-Down DC-DC Converter Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 REG1-REG4 Synchronous Rectification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 REG1/REG2 100% Duty-Cycle Operation (Dropout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Linear Regulators (REG5-REG8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REG5 (VCC_MVT, VCC_BG, VCC_OSC13M, VCC_PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REG6/REG7 (VCC_CARD1, VCC_CARD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 REG8 (VCC_BBATT) Always-On Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ramp-Rate Control (RAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Enable Signals (EN_, PWR_EN, SYS_EN, I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REG3/REG4 Enable (EN34, EN3, EN4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Power-Up and Power-Down Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Marvell PXA3xx Power Configuration Register (PCFR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Voltage Monitors, Reset, and Undervoltage-Lockout Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Undervoltage and Overvoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset Output (RSO) and MR Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Low-Battery Detector, (LBO, LBF, LBR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Internal Off-Discharge Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Thermal-Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Acknowledge Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Slave Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 I2C Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Table of Contents (continued)
Design Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Setting the Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Inductor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Input Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Output Capacitor Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 PCB Layout and Routing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chip Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Tables Table 1. Maxim and Marvell PXA3xx Power Domain Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 2. Maxim and Marvell PXA3xx Digital Signal Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 3. SET1 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 4. SET2 Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 5. Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 6. Truth Table for V3/V4 Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 7. Power Modes and Corresponding Quiescent Operating Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 8. Internal Off-Discharge Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 9. I2C Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 10. DVM Voltage Change Register (VCC1, 0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 11. Serial Codes for V3 (VCC_APPS) and V4 (VCC_SRAM) Output Voltages. . . . . . . . . . . . . . . . . . . . . . 37 Table 12. Serial Codes for V5 Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 13. Serial Codes for V6 and V7 Output Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Figures Figure 1. Example MAX8660 Connection to Marvell PXA3xx Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 2. Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 3. Typical Applications Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 4. Soft-Start and Voltage-Change Ramp Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 5. V3/V4 Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 6. Power-Up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure 7. Low-Battery Detector Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure 8. START and STOP Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 9. Acknowledge Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 10. Slave Address Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Figure 11. Writing to the MAX8660/MAX8661 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
ABSOLUTE MAXIMUM RATINGS
IN, IN5, IN6, IN67, EN2, EN34, EN5, LBO, RSO, MR, SET1, SET2, V1, V2, V3, V4, SCL, SDA, SRAD to AGND..................................................-0.3V to +7.5V LBF, LBR, EN1, RAMP to AGND .................-0.3V to (VIN + 0.3V) V8 to AGND................................................-0.3V to (VIN8 + 0.3V) V5 to AGND................................................-0.3V to (VIN5 + 0.3V) V6, V7 to AGND........................................-0.3V to (VIN67 + 0.3V) PV1 to PG1 ............................................................-0.3V to +7.5V PV2 to PG2 ............................................................-0.3V to +7.5V PV3 to PG3 ............................................................-0.3V to +7.5V PV4 to PG4 ............................................................-0.3V to +7.5V PV, PV1, PV2, PV3, PV4, IN8 to IN ........................-0.3V to +0.3V LX1 Continuous RMS Current (Note 1) .................................2.3A LX2 Continuous RMS Current (Note 1) .................................2.0A LX3 Continuous RMS Current (Note 1) .................................2.6A LX4 Continuous RMS Current (Note 1) .................................1.0A PG1, PG2, PG3, PG4, EP to AGND.......................-0.6V to +0.6V GND to AGND ......................................................-0.3V to +0.3V All REGx Output Short-Circuit Duration......................Continuous Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN (derate 35.7mW/C above +70C).....2857mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Note 1: LX_ has internal clamp diodes to PG_ and PV_. Applications that forward bias these diodes must take care not to exceed the IC's package power-dissipation limits.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER PV1, PV2, PV3, PV4, IN, IN8 Supply Voltage Range IN Undervoltage-Lockout Threshold IN Overvoltage-Lockout Threshold SYMBOL VIN VUVLO VOVLO CONDITIONS PV1, PV2, PV3, PV4, IN, and IN8 must be connected together externally VIN rising VIN falling VIN rising VIN falling Only V8 on (deep-sleep power mode) V1, V2, and V8 on; V1 and V2 in normal (skip) operating mode V1, V2, V5, and V8 on (sleep power mode); V1 and V2 in normal (skip) operating mode V1, V2, V3, V4, V5, and V8 on (run power mode); V1, V2, V3, and V4 in normal (skip) operating mode V1, V2, V3, V4, V5, V6, V7, and V8 (all on); V1, V2, V3, and V4 in normal (skip) operating mode Undervoltage lockout, VIN = 2.2V Overvoltage lockout, VIN = 6.5V MIN 2.6 2.250 2.200 6.20 6.00 2.400 2.350 6.35 6.15 20 TYP MAX 6.0 2.550 2.525 6.50 6.30 UNITS V V V
50
90
Input Current
IIN+ No load; IPV1+IPV2+ SDA = SCL = V8 IPV3+IPV4+ IIN5+ IIN67+ IIN8
A 140
250
1.5 25
4
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER PWM Switching Frequency SYMBOL fSW CONDITIONS MIN 1.9 3.250 2.955 2.807 2.463 1.970 1.773 TYP 2.0 3.300 3.000 2.850 2.500 2.000 1.800 -1.5 0.15 0.01 150 200 0.12 0.15 1.5 1.8 25 Forced-PWM mode only IOUT1 2.6V VPV1 6V (Note 5) VPV1 = 6V, LX1 = PG1 or PV1, VEN1 = 0V TA = +25C TA = +85C 5 3 1.2 5 -2 0.03 0.2 7 5 350 650 Forced-PWM mode only, min duty cycle in skip mode is 0% 16.7 100 9 7 +2 A -975 2.2 MAX 2.1 3.350 3.045 2.893 2.538 2.030 1.827 V UNITS MHz
MAX8660/MAX8660A/MAX8660B/MAX8661
REG1--SYNCHRONOUS STEP-DOWN DC-DC CONVERTER (MAX8660, MAX8660A only) SET1 = IN, VPV1 = 4.2V, load = 600mA V1 Voltage SET1 not connected, VPV1 = 3.6V, V1 Accuracy (MAX8860/MAX8860B) load = 600mA SET1 = AGND, VPV1 = 3.6V, load = 600mA SET1 = IN, VPV1 = 4.2V, load = 600mA V1 Voltage Accuracy (MAX8660A) V1 SET1 not connected, VPV1 = 3.6V, 600mA SET1 = AGND, 3.6V, load = 600mA V1 Load Regulation Load = 0 to 1200mA V1 Line Regulation SET1 Input Leakage Current V1 Dropout Voltage p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold n-Channel Zero-Crossing Threshold n-Channel Negative Current Limit REG1 Maximum Output Current V1 Bias Current LX1 Leakage Current Soft-Start Ramp Rate (MAX8660/MAX8860B) Soft-Start Ramp Rate (MAX8660A) V5 to V1 Enable Time Internal Off-Discharge Resistance Minimum Duty Cycle Maximum Duty Cycle tVMHVSH1 Load = 800mA (Notes 3, 4) Load = 1200mA (Notes 3, 4)
V %/A %/V A mV A mA mA A A
To V1 = 3.3V (total ramp time is 450s for all V1 output voltages) To V1 = 2.5V (total ramp time is 450s for all V1 output voltages) Figure 6
mV/s mV/s s % %
_______________________________________________________________________________________
5
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN 3.250 2.463 1.773 2.463 1.970 1.773 TYP 3.300 2.500 1.800 2.500 2.000 1.800 -1.7 0.15 0.01 Load = 900mA (Notes 3, 4) 225 0.18 0.15 1.10 Forced-PWM mode only IOUT2 2.6V VPV2 6V (Note 5) VPV2 = 6V, LX2 = PG2 or PV2, VEN2 = 0V TA = +25C TA = +85C 2 0.9 5 -2 0.03 0.2 4 350 650 Forced-PWM mode only; min duty cycle in skip mode is 0% 16.7 100 MAX8860/MAX8660A/MAX8661 REG3 default output voltage, VPV3 = 3.6V, load = 600mA V3 Output Voltage Accuracy V3 MAX8860B REG3 default output voltage, VPV3 = 3.6V, load = 600mA REG3 serial programmed from 0.9V to 1.8V, load = 600mA (Note 6) V3 Load Regulation V3 Line Regulation p-Channel On-Resistance n-Channel On-Resistance Load = 0 to 1600mA (Note 7) 6 mV/s s % % +2 A 1.30 25 -800 1.50 MAX 3.350 2.538 1.827 2.538 2.030 1.827 %/A %/V A mV A mA mA A A V V UNITS
REG2--SYNCHRONOUS STEP-DOWN DC-DC CONVERTER SET2 = IN, VPV2 = 4.2V, load = 600mA V2 Voltage Accuracy (MAX8660/MAX8860B) V2 SET2 not connected, VPV2 = 3.6V, load = 600mA SET2 = AGND, VPV2 = 3.6V, load = 600mA SET2 = IN, VPV2 = 4.2V, load = 600mA V2 Voltage Accuracy (MAX8660A) V2 SET2 not connected, VPV2 = 3.6V, load = 600mA SET2 = AGND, VPV2 = 3.6V, load = 600mA V2 Load Regulation V2 Line Regulation SET2 Input Leakage Current V2 Dropout Voltage p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold n-Channel Zero Crossing Threshold n-Channel Negative Current Limit REG2 Maximum Output Current V2 Bias Current LX2 Leakage Current Load = 0 to 900mA
Soft-Start Ramp Rate V5 to V2 Enable Time Internal Off-Discharge Resistance Minimum Duty Cycle Maximum Duty Cycle
To V2 = 1.8V (total ramp time is 450s for all V2 output voltages) tVMHVSH2 Figure 6
REG3--SYNCHRONOUS STEP-DOWN DC-DC CONVERTER 1.379 1.400 1.421 V 1.133 -1.5 -17 0.05 0.12 0.08 1.150 1.167 +1.5 % mV/A %/V
6
_______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER p-Channel Current-Limit Threshold n-Channel Zero-Crossing Threshold n-Channel Negative Current Limit REG3 Maximum Output Current V3 Bias Current LX3 Leakage Current VPV3 = 6V, LX3 = PG3 or PV3, VEN34 = 0V TA = +25C -2 TA = +85C MAX8660/MAX8660A/MAX8661, RRAMP = 56k to 1.4V MAX8660B, RRAMP = 56k to 1.15V RRAMP = 56k MAX8660/MAX8660A/MAX8661, powering up to 1.4V, Figure 6, RRAMP = 56k MAX8660B, powering up to 1.15V, Figure 6, RRAMP = 56k Forced-PWM mode only, min duty cycle in skip mode is 0% IOUT3 Forced-PWM mode only 2.6V VPV3 6V (Note 5) 1.6 0.01 +0.03 0.24 8 6.7 10 400 s 400 550 16.7 100 MAX8660/MAX8660A/MAX8661 REG4 default output voltage, VPV4 = 3.6V, load = 200mA V4 Output Voltage Accuracy V4 MAX8660B REG4 default output voltage, VPV4 = 3.6V, load = 200mA REG4 serial programmed from 0.9V to 1.8V, load = 200mA (Note 6) V4 Load Regulation V4 Line Regulation p-Channel On-Resistance n-Channel On-Resistance p-Channel Current-Limit Threshold n-Channel Zero-Crossing Threshold n-Channel Negative Current Limit REG4 Maximum Output Current V4 Bias Current LX4 Leakage Current VPV4 = 6V, LX4 = PG4 or PV4, VEN34 = 0V TA = +25C TA = +85C -2 IOUT4 Forced-PWM mode only 2.6V VPV4 6V (Note 5) 0.4 0.01 0.02 0.12 8 6.7 10 mV/s +2 0.05 Load = 0 to 400mA (Note 7) % % mV/s +2 SYMBOL CONDITIONS MIN 1.85 TYP 2.15 25 -0.8 MAX 2.45 UNITS A mA A A A A
MAX8660/MAX8660A/MAX8660B/MAX8661
Soft-Start Ramp Rate V3 Dynamic-Change Ramp Rate
mV/s
EN34 to V3 Enable Time
tPHLVTH3
Internal Off-Discharge Resistance Minimum Duty Cycle Maximum Duty Cycle REG4--SYNCHRONOUS STEP-DOWN DC-DC CONVERTER 1.379 1.133 -1.5
1.400 1.150
1.421 V 1.167 +1.5 % mV/A %/V 0.90 A mA mA A A A
-40 0.1 0.37 0.3 0.78 25 -975
Soft-Start Ramp Rate V4 Dynamic-Change Ramp Rate
MAX8660/MAX8660A/MAX8661, RRAMP = 56k to 1.4V MAX8660B, RRAMP = 56k to 1.15V RRAMP = 56k
mV/s
_______________________________________________________________________________________
7
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MAX8660/MAX8660A/MAX8661, powering up to 1.4V, Figure 6, RRAMP = 56k MAX8660B, powering up to 1.15V, Figure 6, RRAMP = 56k Forced-PWM mode only, minimum duty cycle in skip mode is 0% MIN TYP 400 s 400 550 16.7 100 VIN5 V5 REG5 default output voltage, 2.35V VIN5 6V, load = 0 to 200mA REG5 serial programmed from 1.7V to 2.0, 2.35V VIN5 6V, load = 0 to 200mA 10Hz to 100kHz, IOUT5 = 10mA VIN5 = (V5 + 1V), IOUT5 = 10mA, f = 10kHz Powering up to 1.8V (total ramp time is 225s for all V5 output voltages) tSEHVMH Figure 6 RRAMP = 56k 5 2.35 1.764 -2 225 350 160 40 7 290 10 2 VIN67 V6 V7 Setting from 1.8V to 3.3V in 0.1V steps, load = 0 to 300mA 3V mode, load = 300mA (Note 3) IOUT6 IOUT7 VIN67 = 3.6V Powering up to 3.3V, (total ramp time is 450s for all V6/V7 output voltages) 5 2.35 -3 55 750 7 350 Load = 0 to 15mA Load = 30mA Load = 15mA (Note 3) IOUT8 V8 = 2.5V 30 3.168 2.800 3.300 3.2 180 70 1.5 VLBFTH VLBRTH 1.182 1.231 1.200 1.250 1.218 1.268 135 3.432 3.432 9 VIN +3 100 9 1.800 VIN 1.836 +2 500 % % V V % mA VRMS dB mV/s s mV/s k V % mV mA mV/s MAX UNITS
EN34 to V4 Enable Time
tPHLVTH4
Internal Off-Discharge Resistance Minimum Duty Cycle Maximum Duty Cycle REG5 LDO IN5 Input Voltage Range
V5 Output Voltage
V5 Output Current Limit V5 Output-Voltage Noise V5 Power-Supply Rejection V5 Soft-Start Ramp Rate EN5 to V5 Enable Time V5 Dynamic-Change Ramp Rate Internal Off-Discharge Resistance REG6, REG7 LDOs IN67 Input Voltage Range REG6 and REG7 Output Voltage (POR Default to 0V, Set by Serial Input) V6, V7 Dropout Voltage V6, V7 Output Current Limit V6, V7 Soft-Start Ramp Rate Internal Off-Discharge Resistance REG8 ALWAYS-ON LDO V8 Output Voltage V8 Dropout Voltage V8 Output Current Limit Internal Off-Discharge Resistance
IOUT5
V8
V mV mA k V V
LOW-BATTERY DETECTOR (LBF, LBR, LBO) Low-Battery Falling Threshold Low-Battery Rising Threshold
8
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER LBO, RSO Output-High Leakage Current LBO Output Low Level Minimum VIN for LBO Assertion LBO Deassert Delay LBF and LBR Input Bias Current RESET (MR, RSO) RSO Threshold RSO Deassert Delay RSO Output-High Leakage Current RSO Output Low Level Minimum VIN for RSO Assertion MR Input High Level MR Input Low Level MR Input Leakage Current MR Minimum Pulse Width THERMAL-OVERLOAD PROTECTION Thermal-Shutdown Temperature Thermal-Shutdown Hysteresis ENABLE INPUTS (EN1, EN2, EN34, EN5) EN_ Input High Level EN_ Input Low Level EN_ Input Leakage Current I2C LOGIC (SDA, SCL, SRAD) SCL, SDA Input High Voltage SCL, SDA Input Low Voltage SCL, SDA Input Hysteresis SCL, SDA Input Current SDA Output Low Voltage SRAD Input High Level SRAD Input Low Level SRAD Input Leakage Current TA = +25C, IN = AGND, VIN = 6V 2.6V VIN 6V, sinking 3mA 2.6V VIN 6V 2.6V VIN 6V VIN = 6V, TA = +25oC -0.2 1.4 0.4 +0.2 -10 0.1 +10 0.2 1.4 0.4 V V V A V V V A 2.6V VIN 6V 2.6V VIN 6V VIN = 6V, TA = +25C -0.2 1.4 0.4 +0.2 V V A TJ rising +160 15 C C tMR VRSOTH tVBHRSTH Voltage on V8, falling, hysteresis is 5% (typ) Figure 6 VIN = 6V, TA = +25C 2.6V VIN 6V, sinking 3mA VIN = 1V, sinking 100A RSO is forced low when the device is in UVLO 2.6V VIN 6V 2.6V VIN 6V VIN = 6V, TA = +25C -0.2 1 1 1.4 0.4 +0.2 2.1 20 2.2 24 2.3 28 0.2 0.2 0.4 V ms A V V V V A s tVBHBFH SYMBOL CONDITIONS VIN = 6V, TA = +25C 2.6V VIN 6V, sinking 3mA VIN = 1V, sinking 100A LBO is forced low when the device is in UVLO Figure 6 TA = +25C TA = +85C 1 0 -50 3 0 0.5 +50 MIN TYP MAX 0.2 0.2 0.4 UNITS A V V s nA
MAX8660/MAX8660A/MAX8660B/MAX8661
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9
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VIN5 = VIN67 = VIN8 = 3.6V, Figure 3, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 2)
PARAMETER I2C TIMING Clock Frequency Hold Time (Repeated) START Condition CLK Low Period CLK High Period Set-Up Time for a Repeated START Condition DATA Hold Time DATA Set-Up Time Set-Up Time for STOP Condition Bus-Free Time Between STOP and START Maximum Pulse Width of Spikes that Must Be Suppressed by the Input Filter of Both DATA and CLK Signals SYMBOL fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF Figure 8 Figure 9 Figure 9 Figure 8 Figure 8 0.6 1.3 0.6 0.6 0 100 0.6 1.3 CONDITIONS MIN TYP MAX 400 UNITS kHz s s s s s ns s s
50
ns
Note 2: Limits are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed through correlation using statistical quality control (SQC) methods. Note 3: The dropout voltage is defined as VIN - VOUT when VOUT is 100mV below the nominal value of VOUT. Note 4: Dropout voltage (VDO) is a function of the p-channel switch resistance (RPCH) and the inductor resistance (RL). The given values assume RL = 50m for the REG1 inductor and 67m for the REG2 inductor: VDO = ILOAD (RP + RL) Note 5: The maximum output current (IOUT(MAX)) is:
V (1 - D) I LIM - OUT 2 x f xL I OUT(MAX) = (1 - D) 1 + (RN + RL ) 2 x f xL
where: RN = n-channel synchronous rectifier RDS (on) RP = p-channel power switch RDS (on) RL = external inductor ESR IOUT(MAX) = maximum output current provided by the PMIC IOUT(TARGET) = maximum desired output current f = operating frequency minimum L = external inductor value Note 6: Tested at 1.4V default output voltage for the MAX8660, MAX8660A, and MAX8661. Tested at 1.15V default output voltage for the MAX8660B. Note 7: All output voltages are possible in normal mode. In forced-PWM mode, the minimum output voltage is limited by 0.167 x VIN. For example, with VIN = 5.688V, the minimum output is 0.95V.
10
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Typical Operating Characteristics
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
QUIESCENT CURRENT vs. INPUT VOLTAGE
MAX8660/61 toc01
MAX8660/MAX8660A/MAX8660B/MAX8661
SWITCHING FREQUENCY vs. INPUT VOLTAGE
2.4 SWITCHING FREQUENCY (MHz) 2.3 2.2 2.1 2.0 1.9 1.8 1.7 1.6 1.5
MAX8660 toc02
100 90 80 INPUT CURRENT (A) 70 60 50 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 SDA = SDL = V8 REG1-REG7 DISABLED REG8 IS ALWAYS ON
2.5
6.0
2.5
3.0
3.5 4.0 4.5 5.0 INPUT VOLTAGE (V)
5.5
6.0
SWITCHING FREQUENCY vs. TEMPERATURE
MAX8660 toc03
EN1/EN2/EN5 ENABLE RESPONSE
MAX8660 toc04
2.3 2.2 2.1
EN1/EN2/EN5
5V/div
SWITCHING FREQUENCY (MHz)
1V/div V2 1V/div V5
2.0 1.9 1.8 1.7 -40 -15 10 35 TEMPERATURE (C) 60 85 100s/div
1V/div
V1
EN34 ENABLE RESPONSE
MAX8660 toc05
EN34
2V/div
500mV/div
V3 500mV/div V4 MAX8660 100s/div RRAMP = 56k
______________________________________________________________________________________
11
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG1 EFFICIENCY vs. LOAD CURRENT
95 90 EFFICIENCY (%) 85 80 75 70 65 60 55 50 0.01 0.1 1 10 100 1000 10,000 LOAD CURRENT (mA) VIN = 4.2V VIN = 3.6V V1 = 3.3V L1 = 1.2H (TOKO DE2812C) FORCED-PWM NORMAL
MAX8660 toc06
REG1 OUTPUT VOLTAGE vs. INPUT VOLTAGE
DROPOUT ILOAD = 10mA
MAX8660 toc07
REG1 LINE TRANSIENT
MAX8660 toc08
100
3.6 3.4 OUTPUT VOLTAGE (V) 3.2 3.0 2.8 2.6 2.4
5.0V VIN 3.6V 1V/div
ILOAD = 1000mA
V1 600mA LOAD, V1 = 3.3V 6.0 40s/div
100mV/div
3.3V OUTPUT 2.2 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5
REG1 LOAD REGULATION
MAX8660 toc09
REG1 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc10
REG1 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8660 toc11
3.40 3.38 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 0
3.40 3.38 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 3.30 3.28 3.26 3.24
VIN = 3.8V
300 250 DROPOUT VOLTAGE (mV) 200 150 100 50
THE NOMINAL ESR OF TOKO'S 1.2 H DE2812C INDUCTOR IS 44m. THE NOMINAL p-CHANNEL RESISTANCE OF THE REG1 IS 120m. THE SLOPE OF THIS LINE SHOWS THAT THE TOTAL REG1 DROPOUT RESISTANCE OF AN AVERAGE PART, BOARD, INDUCTOR COMBINATION IS 172m.
-1.5%/A
FORCED-PWM NORMAL 200 400 600 800 LOAD CURRENT (mA) 1000 1200
3.22 3.20 -40 -15
600mA LOAD 0 10 35 TEMPERATURE (C) 60 85 0 200 400 600 800 LOAD CURRENT (mA) 1000 1200
REG1 LOAD TRANSIENT
MAX8660 toc12
REG 1 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8660 toc13
REG1 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc14
V1
V1 = 3.3V 3.8V INPUT 100mV/div VLX1 2V/div VLX1 2V/div
V1 800mA IV1 10mA 500mV/div IL1 4.2V INPUT 1A LOAD 40s/div 400ns/div
2mV/div
V1 20mV/div
1A/div 0A
IL1
200mA/div 0A 3.8V INPUT, 20mA LOAD 2s/div
12
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG2 EFFICIENCY vs. LOAD CURRENT
90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 0.01 0.1 1 10 100 LOAD CURRENT (mA) 1000 L2 = 2.0H (TOKO DE2812C) V2 = 1.8V 1.65 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 VIN = 4.2V VIN = 3.6V FORCED-PWM NORMAL
MAX8660 toc15
MAX8660/MAX8660A/MAX8660B/MAX8661
REG2 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8660 toc16
REG2 LINE TRANSIENT
MAX8660 toc17
95
1.95 1.90 10mA LOAD OUTPUT VOLTAGE (V) 1.85 1.80 1.75 1.70 800mA LOAD
5.0V VIN 3.6V 1V/div
V2 450mA LOAD, V2 = 1.8V 40s/div
100mV/div
REG2 LOAD REGULATION
MAX8660 toc18
REG2 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc19
REG2 DROPOUT VOLTAGE vs. LOAD CURRENT
THE NOMINAL ESR OF TOKO'S 2.0 H DE2812C INDUCTOR IS 67m. THE NOMINAL p-CHANNEL RESISTANCE OF THE REG2 IS 180m. THE SLOPE OF THIS LINE SHOWS THAT THE TOTAL REG2 DROPOUT RESISTANCE OF AN AVERAGE PART, BOARD, INDUCTOR COMBINATION IS 255m.
MAX8660 toc20
1.85 VIN = 3.6V 1.83 OUTPUT VOLTAGE (V) -1.7%/A 1.81
1.90 1.88 1.86 OUTPUT VOLTAGE (V) 1.84 1.82 1.80 1.78 1.76 1.74 800mA LOAD
300 250 DROPOUT VOLTAGE (mV) 200 150 100 50 0
1.79
1.77 FORCED-PWM NORMAL 1.75 0 200 400 600 LOAD CURRENT (mA) 800
1.72 1.70 -40 -15 10 35 TEMPERATURE (C) 60 85 0 200 400 600 800 LOAD CURRENT (mA) 1000
REG2 LOAD TRANSIENT
MAX8660 toc21
REG2 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8660 toc22
REG2 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc23
VLX2 V2 100mV/div
2V/div
VLX2
2V/div
600mA V2
2mV/div V2
20mV/div
IV2 10mA V2 = 1.8V 20s/div
200mA/div
IL2 800mA LOAD 400ns/div
1A/div 0A
IL2 30mA LOAD 2s/div
200mA/div 0A
______________________________________________________________________________________
13
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG3 EFFICIENCY vs. LOAD CURRENT
85 80 EFFICIENCY (%) 75 70 65 60 55 50 0.01 0.1 1 10 100 LOAD CURRENT (mA) 1000 10,000 VIN = 3.6V V3 = 1.4V L3 = 1.2H (TOKO DE2812C) VIN = 4.2V FORCED-PWM NORMAL
MAX8660 toc24
REG3 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8660 toc25
REG3 LINE TRANSIENT
MAX8660 toc26
90
1.45 1.44 1.43 OUTPUT VOLTAGE (V) 1.42 1.41 1.40 1.39 1.38 1.37 1.36 1.35 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 ILOAD = 1000mA
5.0V VIN 3.6V 1V/div
V3 800mA LOAD, V3 = 1.4V 6.0 40s/div
50mV/div
REG3 LOAD REGULATION
MAX8660 toc27
REG3 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc28
REG3 VOLTAGE CHANGE RESPONSE
MAX8660 toc29
1.44 1.43 OUTPUT VOLTAGE (V) 1.42 VIN = 3.6V FORCED-PWM NORMAL
1.50 1.48 1.46 OUTPUT VOLTAGE (V) 1.44 1.42 1.40 1.38 1.36 1.34
RRAMP = 56k V3 RISING 0.725V
1.8V 500mV/div RRAMP = 248k
1.41 1.40 1.39 1.38 1.37 1.36 0 200 400 600 800 1000 1200 1400 1600 LOAD CURRENT (mA)
1.8V V3 FALLING RRAMP = 56k ILOAD = 1000mA -40 -15 10 35 TEMPERATURE (C) 60 85 ACTIVE RAMP-DOWN ENABLED 100s/div RRAMP = 248k 500mV/div 0.725V
1.32 1.30
REG3 LOAD TRANSIENT
MAX8660 toc30
REG3 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8660 toc31
REG3 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc32
V3
50mV/div
VLX3
2V/div
VLX3
2V/div
900mA
V3 IL3
2mV/div
V3
20mV/div
IV3
10mA
500mV/div 1500mA LOAD 20s/div 400ns/div
1A/div 0A
IL3
200mA/div 0A 30mA LOAD 2s/div
14
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG4 EFFICIENCY vs. LOAD CURRENT
MAX8660 toc33
REG4 OUTPUT VOLTAGE vs. INPUT VOLTAGE
ILOAD = 300mA 1.41 OUTPUT VOLTAGE (V) 1.40 1.39 1.38 1.37 1.36 V4
MAX8660 toc34
REG4 LINE TRANSIENT
MAX8660 toc35
95 90 85 EFFICIENCY (%) 80 75 70 65 60 55 50 0.01 0.1 1 10 100 LOAD CURRENT (mA) L4 = 4.7H (TOKO DE2812C) V4 = 1.4V VIN = 4.2V VIN = 3.6V FORCED-PWM NORMAL
1.42
5.0V VIN 3.6V 1V/div
10mV/div
200mA LOAD, V5 = 1.4V 1.35 1000 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 40s/div
REG4 LOAD REGULATION
MAX8660 toc36
REG4 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc37
REG4 VOLTAGE CHANGE RESPONSE
MAX8660 toc38
1.44 1.43 OUTPUT VOLTAGE (V) 1.42 VIN = 3.6V FORCED-PWM NORMAL
1.50 400mA LOAD 1.45 OUTPUT VOLTAGE (V) 1.40 1.35 1.30 1.25 1.20
RRAMP = 56k V4 RISING 0.725V
1.8V 500mV/div RRAMP = 248k
1.41 1.40 1.39 1.38 1.37 1.36 0 100 200 300 LOAD CURRENT (mA) 400
1.8V V4 FALLING RRAMP = 56k ACTIVE RAMP-DOWN ENABLED -40 -15 10 35 TEMPERATURE (C) 60 85 100s/div RRAMP = 248k 500mV/div 0.725V
REG4 LOAD TRANSIENT RESPONSE
MAX8660 toc39
REG4 HEAVY-LOAD SWITCHING WAVEFORMS
MAX8660 toc40
REG4 LIGHT-LOAD SWITCHING WAVEFORMS
MAX8660 toc41
VLX4 V4 50mV/div
2V/div VLX4 2V/div
V4 350mA IL4 IV4 10mA 200mV/div 20s/div 400ns/div
2mV/div
V4
20mV/div
200mA/div I L4 200mA LOAD 0A 2s/div 18mA LOAD
200mA/div 0A
______________________________________________________________________________________
15
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG5 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8660 toc42
REG5 OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8660 toc43
REG5 OUTPUT VOLTAGE vs. TEMPERATURE
100mA LOAD 1.82 OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77
MAX8660 toc44
1.83 100mA LOAD 1.82 OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5
1.83 1.82 OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77
1.83
6.0
0
50
100 150 LOAD CURRENT (mA)
200
-40
-15
10 35 TEMPERATURE (C)
60
85
REG5 LINE TRANSIENT
MAX8660 toc45
REG5 LOAD TRANSIENT RESPONSE
MAX8660 toc46
REG5 VOLTAGE CHANGE RESPONSE
MAX8660 toc47
100mA LOAD VIN 3.6V
5.0V V5 1V/div 50mV/div RRAMP = 56k 2.0V 100mV/div V5 20mV/div 1.725V IV5 180mA 10mA 100mA LOAD, V5 = 1.8V 20s/div
V5 100mA LOAD, V5 = 1.8V 40s/div
100mA/div 40s/div
REG5 OUTPUT NOISE SPECTRAL DENSITY vs. FREQUENCY
MAX8660 toc48
REG5 OUTPUT NOISE (0.1Hz TO 10Hz)
MAX8660 toc49
REG5 PSRR vs. FREQUENCY
RLOAD = 180 70 60
MAX8660 toc50
10,000
80
NOISE DENSITY (nV/(Hz))
1000 PSRR (dB) 10V/div 100
50 40 30 20 10
10 0.01 0.1 1 10 FREQUENCY (kHz) 100 1s/div
0 0.01 0.1 1 10 FREQUENCY (kHz) 100
16
______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG6/REG7 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8660 toc51
MAX8660/MAX8660A/MAX8660B/MAX8661
REG6/REG7 OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8660 toc52
REG6/REG7 OUTPUT VOLTAGE vs. TEMPERATURE
1.88 1.86 OUTPUT VOLTAGE (V) 1.84 1.82 1.80 1.78 1.76 1.74 300mA LOAD
MAX8660 toc53
1.83 1.82 OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77
100mA LOAD
3.5
1.90
3.0 OUTPUT VOLTAGE (V) 4.2V INPUT 3.3V OUTPUT 2.5
2.0
1.5 2.4V INPUT 1.8V OUTPUT 1.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 0 100 200 300 400 500 600 700 800 900 LOAD CURRENT (mA)
1.72 1.70 -40 -15 10 35 TEMPERATURE (C) 60 85
REG6/REG7 LINE TRANSIENT
MAX8660 toc54
REG6/REG7 LOAD TRANSIENT
MAX8660 toc55
5.0V VIN 3.6V 1V/div V6/V7 50mV/div
300mA
V6/V7
20mV/div
IV6/IV7 10mA
100mA/div
300mA LOAD, V6/V7 = 1.8V 40s/div
V6/V7 = 1.8V 10s/div
REG6/REG7 ENABLE WAVEFORM
MAX8660 toc56
REG6/REG7 DROPOUT OUTPUT VOLTAGE vs. LOAD CURRENT
2V/div DROPOUT VOLTAGE (mV) THE SLOPE OF THESE LINES SHOWS THAT THE REG6/REG7 DROPOUT RESISTANCE OF AN AVERAGE PART MOUNTED ON THE MAXIM EVALUATION KIT IS 205m. 3.0V OUTPUT
MAX8660 toc57
140 120 100 80 60 40 20 0
I2C ENABLE SIGNAL VSDA
60s
500mV/div V6/V7
3.3V OUTPUT
100s/div
0
100
200 300 400 LOAD CURRENT (mA)
500
______________________________________________________________________________________
17
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Typical Operating Characteristics (continued)
(Circuit of Figure 3, VIN = 3.6V, TA = +25C, unless otherwise noted.)
REG8 OUTPUT VOLTAGE vs. INPUT VOLTAGE
3.4 3.2 OUTPUT VOLTAGE (V) 3.0 2.8 2.6 2.4 2.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 6.0 V8 (V) 5mA LOAD
MAX8660 toc58
REG8 LOAD REGULATION
3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 2.0 0 10 20 30 40 50 60 LOAD CURRENT (mA) 70 80 VIN = 3.6V
MAX8660 toc59 MAX8660 toc61
4.0
REG8 OUTPUT VOLTAGE vs. TEMPERATURE
MAX8660 toc60
REG8 LINE TRANSIENT
5.0V VIN 3.6V 1V/div
3.40 3.38 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 3.30 3.28 3.26 3.24 3.22 3.20 -40 -15 10 35 TEMPERATURE (C) 60 5mA LOAD
50mV/div V8
10mA LOAD 85 40s/div
REG8 LOAD TRANSIENT
MAX8660 toc62
REG8 DROPOUT VOLTAGE vs. LOAD CURRENT
350 DROPOUT VOLTAGE (mV) 50mV/div 300 250 200 150 100 50 0 0 5 10 15 20 LOAD CURRENT (mA) 25 30 THE SLOPE OF THIS LINE SHOWS THAT THE REG8 DROPOUT RESISTANCE OF AN AVERAGE PART MOUNTED ON THE MAXIM EVALUATION KIT IS 12.4.
MAX8660 toc63
400
V8
15mA IV8 5mA 10mA/div
10s/div
18
______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Pin Description
PIN MAX8660 MAX8861 NAME FUNCTION REG5 Power Input. Connect IN5 to IN to ensure V5 rises first to meet the Marvell PXA3xx processor's sequencing requirements. If adherence to this sequencing specification is not required, connect IN5 to V1, V2, or another supply between 2.35V and VIN. See the Linear Regulators (REG5-REG8) section for more information. REG5 Linear-Regulator Output. V5 defaults to 1.8V and is adjustable from 1.7V to 2.0V through the serial interface. The input to the V5 regulator is IN5. Use V5 to power VCC_MVT, VCC_BG, VCC_OSC13M, and VCC_PLL on Marvell PXA3xx processors. V5 is internally pulled to AGND through 2k when REG5 is shut down. REG4 Power Input. Connect a 4.7F ceramic capacitor from PV4 to PG4. All PV pins and IN must be connected together externally. REG4 Switching Node. Connect LX4 to the REG4 inductor. LX4 is high impedance when REG4 is shut down. REG4 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit data sheet for more information. REG2 Voltage Select Input. SET2 is a tri-level logic input. Connect SET2 to select the V2 output voltage as detailed in Table 4. The REG2 output voltage selected by SET2 is latched at the end of the REG2 soft-start period. Changes to SET2 after the startup period have no effect. REG6 Linear-Regulator Output. REG6 is activated and programmed through the serial interface to output from 1.8V to 3.3V in 0.1V steps. REG6 is off by default. V6 is internally pulled to AGND through 350 when REG6 is shut down. V6 optionally powers VCC_CARD1 on Marvell PXA3xx processors. REG6 and REG7 Power Input. IN67 is typically connected to IN. IN67 can also be connected to any supply between 2.35V to VIN. REG6 Power Input. IN6 is typically connected to IN. IN6 can also be connected to any supply between 2.35V to VIN. REG7 Linear-Regulator Output. REG7 is activated and programmed through the serial interface to output from 1.8V to 3.3V in 0.1V steps. REG7 is off by default. V7 is internally pulled to AGND through 350 when REG7 is shut down. V7 optionally powers VCC_CARD2 on Marvell PXA3xx processors. No Internal Connection REG2 Voltage Sense Input. Connect V2 directly to the REG2 output voltage. The output voltage of REG2 is selected by SET2. V2 is internally pulled to AGND through 650 when REG2 is shut down. V2 powers VCC_MEM on Marvell PXA3xx processors. Serial-Clock Input. See the I 2C Interface section. Serial-Data Input. See the I 2C Interface section. Low-Battery Output. LBO is an open-drain output that pulls low when LBF is below its threshold. LBO typically connects to the nBATT_FAULT input of the applications processor to indicate that the battery has been removed or discharged. REG2 Power Input. Connect a 4.7F ceramic capacitor from PV2 to PG2. All PV pins and IN must be connected together externally. REG2 Switching Node. Connect LX2 to the REG2 inductor. LX2 is high impedance when REG2 is shut down.
1
1
IN5
--
2
V5
3 4 5
3 4 5
PV4 LX4 PG4
6
6
SET2
7
7
V6
8 --
-- 8
IN67 IN6
9
--
V7
-- 10 11 12 13
9 10 11 12 13
N.C. V2 SCL SDA LBO
14 15
14 15
PV2 LX2
______________________________________________________________________________________
19
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Pin Description (continued)
PIN MAX8660 MAX8661 16 17 18 19 16 17 18 19 NAME PG2 IN8 IN AGND FUNCTION REG2 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit data sheet for more information. REG8 Input Power Connection. IN8 must be connected to IN. Main Battery Input. This input provides power to the IC. Connect a 0.47F ceramic capacitor from IN to AGND. Analog Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit data sheet for more information. REG8 Always-On 3.3V LDO Output. REG8 is the first regulator that powers up in the MAX8660/MAX8661. REG8 is supplied from IN and supplies up to 30mA. V8 is internally pulled to AGND through 1.5k during IN undervoltage or overvoltage lockout. Connect V8 to VCC_BBATT on Marvell PXA3xx processors. Low-Battery Detect Falling Input. The LBF threshold is 1.20V. Connect LBF to LBR for 50mV hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBF sets the falling voltage at which LBO goes low. See the Low-Battery Detector (LBO, LBF, LBR) section for more information. Low-Battery Detect Rising Input. The LBR threshold is 1.25V. Connect LBF to LBR for 50mV hysteresis. Use a three-resistor voltage-divider for larger hysteresis. LBR sets the rising voltage at which LBO goes high. See the Low-Battery Detector (LBO, LBF, LBR) section for more information. Manual Reset Input. A low MR input causes RSO to go low and resets all serial programmed registers to their default values. See the Reset Output (RSO) and MR Input section for more information. Ramp-Rate Input. Connect a resistor from RAMP to AGND to set the regulator ramp rates. See the Ramp-Rate Control (RAMP) section for more information. REG5 Enable Input. Drive EN5 high to turn on REG5. EN5 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. EN5 is typically driven by the SYS_EN output of an Marvell PXA3xx processor. REG3 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit data sheet for more information. REG3 Switching Node. Connect LX3 to the REG3 inductor. LX3 is high impedance when REG3 is shut down. REG3 Power Input. Connect a 4.7F ceramic capacitor from PV3 to PG3. All PV pins and IN must be connected together externally. Open-Drain Reset Output. RSO typically connects to the nRESET input on an applications processor. An output low from the MAX8660/MAX8661 RSO resets all serial programmed registers to their default values and causes the processor to enter its reset state. See the Reset Output (RSO) and MR Input section for more information. REG3 Voltage Sense Input. Connect V3 directly to the REG3 output voltage. The output voltage is adjustable from 0.725V to 1.8V through the serial interface. V3 is internally pulled to AGND through 550 when REG3 is shut down. V3 connects to VCC_APPS on Marvell PXA3xx processors. REG3 and REG4 Active-High Hardware Enable Input. Drive EN34 high to enable both REG3 and REG4. Drive EN34 low to allow the serial interface to enable REG3 and REG4 independently. EN34 has hysteresis so an RC can be used to implement manual sequencing with respect to other inputs. EN34 is typically driven by the PWR_EN output of an Marvell PXA3xx processor. See the REG3/REG4 Enable (EN34, EN3, EN4) section for more information.
20
20
V8
21
21
LBF
22
22
LBR
23
23
MR
24
24
RAMP
25
25
EN5
26 27 28
26 27 28
PG3 LX3 PV3
29
29
RSO
30
30
V3
31
31
EN34
20
______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Pin Description (continued)
PIN MAX8660 MAX8661 32 32 NAME FUNCTION REG2 Enable Input. Drive EN2 high to turn on REG2. EN2 has hysteresis so that an RC can be used to implement manual sequencing with respect to other inputs. EN2 is typically driven by the SYS_EN output of an Marvell PXA3xx processor. Serial-Address Input. Connect SRAD to AGND for a 7-bit slave address of 0110 100 (0x68). Connect SRAD to IN to change the address to 0110 101 (0x6A). The eighth slave address bit is always zero since the MAX8660/MAX8661 are write-only. See the Slave Address section for more information. REG1 Power Ground. Connect PG1, PG2, PG3, PG4, and AGND together. Refer to the MAX8660 EV kit data sheet for more information. Ground. Connect all GND pins to EP. REG1 Switching Node. Connect LX1 to the REG1 inductor. LX1 is high impedance when REG1 is shutdown. No Internal Connection REG1 Power Input. Connect a 4.7F ceramic capacitor from PV1 to PG1. All PV pins and IN must be connected together externally. Power Input. All PV pins and IN must be connected together externally. REG1 Enable Input. Drive EN1 high to turn on REG1. EN1 has hysteresis so that an RC can be used to implement manual sequencing with respect to other inputs. EN1 is typically driven by the SYS_EN output of an applications processor. Ground. Connect all GND pins to EP. REG1 Voltage Sense Input. Connect V1 directly to the REG1 output voltage. The output voltage of REG1 is selected by SET1. Connect V1 to VCC_IOx of the applications processor. V1 is internally pulled to AGND through 650 when REG1 is shut down. Ground. Connect all GND pins to EP. REG1 Voltage Select Input. SET1 is a tri-level logic input. Connect SET1 to select the V1 output voltage as detailed in Table 3. The REG1 output voltage selected by SET1 is latched at the end of the REG1 soft-start period. Changes to SET1 after the startup period have no effect. Ground. Connect all GND pins to EP. REG4 Feedback Sense Input. Connect V4 directly to the REG4 output voltage. The REG4 output voltage is adjustable from 0.725V to 1.8V with the serial interface. V4 is internally pulled to AGND through 550 when REG4 is shut down. V4 powers VCC_SRAM on the applications processor. Exposed Pad. Connect the exposed pad to ground. Connecting the exposed pad to ground does not remove the requirement for proper ground connections to PG1, PG2, PG3, PG4, and AGND. The exposed pad is attached with epoxy to the substrate of the die, making it an excellent path to remove heat from the IC.
EN2
33
33
SRAD
34 -- 35 -- 36 -- 37 -- 38 -- 39 -- 40
-- 34 -- 35 -- 36 -- 37 -- 38 -- 39 40
PG1 GND LX1 N.C. PV1 PV EN1 GND V1 GND SET1 GND V4
--
--
EP
______________________________________________________________________________________
21
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
V1 3.3V AT 1200mA 15mA 5mA 1045mA AUXILIARY POWER PERIPHERALS 10mA VCC_I01 VCC_I03 VCC_I04 VCC_I06 VCC_LCD VCC_MSL VCC_DF VCC_CI VCC_MEM VCC_USB VCC_TSI MARVELL PXA3xx PROCESSOR
MAX8660
135mA
25mA 50mA 50mA 55mA 20mA 160mA 50mA 35mA V2 1.8V AT 900mA 540mA V3 0.725V TO 1.8V AT 1600mA V4 0.725V TO 1.8V AT 400mA 40mA 200mA AUXILARY POWER PERIPHERALS MEMORY 1600mA 360mA AUXILIARY POWER
IN
VCC_APPS VCC_SRAM
VCC_MVT VCC_BG V5 1.7V TO 2.0V (DEF 1.8V) AT 200mA VCC_OSC13M VCC_PLL V6 1.8V TO 3.3V (DEF 0V) AT 500mA 485mA V7 1.8V TO 3.3V (DEF 0V) AT 500mA 485mA V8 3.3V AT 30mA 25mA I2C EN1 EN2 EN5 EN34 V8 (VCC_BBATT) 15mA SD/CF MEMORY CARD 1 15mA SD/CF MEMORY CARD 2 5mA AUXILIARY POWER STANDARD I2C POWER I2C SDA {GPIO33} SCL {GPIO32} PWR_SDA PWR_SCL SYS_EN PWR_EN VCC_BBATT VCC_CARD2 VCC_CARD1
RSO LBO
nRESET nBATT_FAULT
Figure 1. Example MAX8660 Connection to Marvell's PXA3xx Processor. This is one example only. Other connections are also supported.
22 ______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
BATT IN REF 1.25V
PV1
BATTERY LBF (1.20V) UVLO OVLO AND BATT MON TO ALL BLOCKS OPEN-DRAIN LOW BATT OUT TO nBATT_FAULT LBO MAX8660 MAX8661 LX1 STEP-DOWN PWM REG1 ON PWM
TO BATT
LBR (1.25V)
PG1 V1 SET1
V1, VCC_I0x, VCC_LCD, VCC_MSL, VDD_USB, VCC_DF, VDD_CI, VCC_TSI MAX8660/MAX8660B; 3.3V, 3.0V, 2.85V MAX8660A; 2.5V, 2.0V, 1.8V 1200mA (MAX8660/MAX8660A/MAX8660B ONLY)
LATCH
AGND
PV2 EN1 FROM CPU SYS_EN TO IN V8, VCC_BBATT (3.3V 30mA, ALWAYS ON) EN2 IN8 V8 ON LX2 STEP-DOWN PWM REG2 LDO REG 8 HARDWARE RESET INPUT TO CPU nRESET MR RSO
TO BATT
PG2 V2 SET2 PV3
V2, VCC_MEM MAX8660/MAX8660B/MAX8661; 3.3V, 2.5V, 1.8V MAX8660A; 2.5V, 2.0V, 1.8V 900mA
PWM
LATCH RESET V8 < 2.4V 20ms STEP-DOWN PWM REG3 RAMP
TO BATT
LX3
RAMP
SET RATE RAMP
ADJ 0.725V TO 1.8V PWM LDO REG 6 ON
PG3 V3
V3, VCC_APPS 0.725V TO 1.8V (DEFAULT 1.4V) for MAX8660/MAX8660A/MAX8661 (DEFAULT 1.15V for MAX8660B) 1.6A
V6, VCC_CARD1 0V/1.8-3.3V (DEFAULT 0V) 500mA
V6
LOGICAL OR (FIGURE 5) IN67 (IN6) STEP-DOWN PWM REG4 RAMP LDO REG 7 ADJ 0.725V TO 1.8V PWM
EN34 PV4
FROM CPU PWR_EN TO BATT
TO V1, V2, OR IN V7, VCC_CARD2 0V/1.8-3.3V (DEFAULT 0V) 500mA (MAX8660/MAX8660A ONLY)
V7
LX4
PG4 V4
V4, VCC_SRAM 0.725V TO 1.8V (DEFAULT 1.4V) for MAX8660/MAX8660A/MAX8661 (DEFAULT 1.15V for MAX8660B) 400mA
VCC_IOx
IN5 ADJ 1.7V TO 2.0V RAMP LDO REG 5 EN5 SRAD EP ( ) ARE FOR THE MAX8661 AGND PGND FROM CPU SYS_EN V5
TO IN, V1 OR V2 V5, VCC_MVT, VCC_BG, 1.7V TO 2.0V (DEFAULT 1.8V) 200mA
SCL SDA I2C SERIAL INTERFACE
Figure 2. Functional Diagram
______________________________________________________________________________________ 23
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
2.6V TO 6.0V INPUT IN R10 20 C22 0.47F 21 LBF R2 80.6k 22 LBR V8 R3 1M 19 AGND PV2 13 37 EN1 EN2 EN34 EN5 SET1 SET2 32 31 25 39 6 33 C21 0.1F V8 V8 R6 300k MR S1 V8 R7 300k 29 RSO 24 R4 56k 12 11 RSO RAMP SDA SCL V7 9 C16 4.7F 2 7 8 IN C20 1F C17 4.7F V7 C13 2.2F V6 23 MR C10 0.1F EN1 EN2 V2 EN34 EN5 SET1 LX3 SET2 SRAD PG3 V3 PV4 27 26 30 3 IN C18 4.7F 4 5 40 IN IN5 1 C19 1F V5 V5 V6 IN67 C8 10F C9 10F L4 4.7H V4 C3 10F C4 10F C5 10F PV3 28 10 IN C12 4.7F L3 1.2H V3 LX2 PG2 LBO 15 16 C7 10F C6 10F U1 18 IN IN PV1 36 C11 4.7F 35 34 38 14 IN C15 4.7F L2 2.0H V2 C1 10F C2 10F L1 1.2H V1
R1 1.82M
MAX8660 MAX8660A MAX8660B
LX1 PG1 V1
R5 300k LBO
IN 17 20 IN8 V8 LX4 PG4 V4
SDA SCL
EP
AGND
PGND
NOTE: REFERENCE DESIGNATORS MATCH MAX8660EVKIT
Figure 3. Typical Applications Circuit
24 ______________________________________________________________________________________
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Detailed Description
The MAX8660/MAX8661 PMICs are optimized for devices using the applications processors, including smart cellular phones, PDAs, Internet appliances, and other portable devices requiring substantial computing and multimedia capability and low power consumption. The MAX8660/MAX8661 comply with Marvell PXA3xx and PXA168 processor specifications. As shown in Figure 2, the MAX8660 integrates eight high-performance, low-operating-current power supplies. REG1-REG4 are step-down DC-DC converters, and REG5-REG8 are linear regulators. Other functions include low-battery detection (LBO), a reset output (RSO), a manual reset input (MR), and a 2-wire I2C serial interface. The MAX8661 functions the same as the MAX8660, but does not have the REG1 step-down regulator and the REG7 linear regulator. The operating input voltage range is from 2.6V to 6.0V, allowing use with a 1-cell Li+ battery, 3-cell NiMH, or a 5V input. Input protection is provided with undervoltage and overvoltage lockouts. Overvoltage lockout protects the device against inputs up to 7.5V.
Maxim vs. Marvell PXA3xx Terminology
The MAX8660/MAX8661 are compatible with Marvell`s PXA3xx processor. Figure 1 shows one of many possible connections between the PXA3xx processor and the MAX8660/MAX8661. To facilitate system development with PXA3xx processors, this document uses both Maxim and Marvell terminology. Marvell terminology appears in parentheses and italics. For example, this document refers to "V8 (VCC_BBATT)" because the MAX8660 V8 output powers the Marvell VCC_BBATT power domain. Tables 1 and 2 outline Maxim and Marvell terminology.
Table 1. Maxim and Marvell PXA3xx Power Domain Terminology
POWER DOMAIN VCC_IO1 VCC_IO3 VCC_IO4 VCC_IO6 VCC_LCD VCC_MSL VCC_CI VCC_DF VCC_MEM VCC_APPS VCC_SRAM VCC_MVT VCC_BG VCC_OSC13M VCC_PLL VCC_CARD1 POWER DOMAIN ACCEPTABLE VOLTAGE 1.8V 10% or 3.0V 10% or 3.3V 10% COMPATIBLE MAXIM POWER DOMAIN DESCRIPTION * Peripheral I/O supply for UARTs, standard I2C, power I2C, audio interface, SSPs, PWMs, etc. (VCC_IO1,VCC_IO3, VCC_IO4, VCC_IO6) * * * * LCD interface logic (VCC_LCD) Fast serial interface (VCC_MSL) Camera flash interface (VCC_CI) Data flash interface (VCC_DF)
V1 or V2
1.8V 10% or 3.0V 10% 1.8V 100mV 0.95V to 1.41V 5% 1.08V to 1.41V 100mV 1.8V 100mV 1.8V 10% or 3.0V 10% or 3.3V 10% 1.8V 10% or 3.0V 10% or 3.3V 10% 3.0V 1V 3.3V 300mV 3.3V 300mV
V1 or V2
V2 V3 V4
* I/O supply for high-speed memory * Main processor core * Internal SRAM memory * * * * Internal logic and I/O blocks (VCC_MVT) Bandgap reference (VCC_BG) 13MHz oscillator (VCC_OSC13M) Phase-locked loop (PLL) and oscillator (VCC_PLL)
V5
V6
* Removable storage and USIM card supply
VCC_CARD2 VCC_BBATT VCC_USB VCC_TSI
V7 V8 V1 or V2 (if programmed to 3.3V) V1 or V2 (if programmed to 3.3V)
* Removable storage and USIM card supply * Regulated battery voltage * Universal serial bus (VCC_USB) * Touch-screen interface (VCC_TSI)
______________________________________________________________________________________
25
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Table 2. Maxim and Marvell PXA3xx Digital Signal Terminology
MAXIM EN34 MARVELL PWR_EN DESCRIPTION Active-High Enable Signal for Processor Core Power. The applications processor drives this PWR_EN signal high to exit sleep mode. The processor's PWR_EN logic is powered by the MAX8660/MAX8661 "always on" V8 (VCC_BBATT) regulator during sleep mode. Active-High Enable Signal for Peripheral Power Supplies. The applications processor drives this SYS_EN signal high to enter run mode. Active-Low Reset. The MAX8660/MAX8661 drive this signal low to reset the processor. When RSO goes low, the MAX8660/MAX8661 I2C registers are reset to their default values. Active-Low Battery Fault. The MAX8660/MAX8661 drive this signal low to signal the processor that the battery has been removed or discharged. I2C Serial-Data Input/Output. The MAX8660/MAX8861 SDA generally connects to both the Marvell PXA3xx processor's standard I2C data line (GPIO33) and its dedicated power I2C data line. This connection operates as an I2C multimaster system with the MAX8660/MAX8661 accepting commands from both the standard I2C and the power I2C. I2C Serial Clock. The MAX8660/MAX8661 SCL generally connects to both the Marvell PXA3xx processor's standard I2C clock line (GPIO32) and its dedicated power I2C clock line. This connection operates as an I2C multimaster system with the MAX8660/MAX8661 accepting commands from both the standard I2C and the power I2C.
EN1, EN2, EN5 RSO LBO
SYS_EN nRESET nBATT_FAULT
SDA
GPIO33 PWR_SDA
SCL
GPIO32 PWR_SCL
Step-Down DC-DC Converters (REG1-REG4)
REG1 (VCC_IO) Step-Down DC-DC Converter (MAX8660 Only) REG1 is a high-efficiency (REG1 + REG8 IQ = 40A) 2MHz current-mode step-down converter that outputs up to 1200mA with efficiency up to 96% (see the Typical Operating Characteristics). The output voltage (V1) is selected with the SET1 input as shown in Table 3. The REG1 output voltage selection is latched at the end of the REG1 soft-start period. Changes in SET1 after the startup period have no effect. EN1 is a dedicated enable input for REG1. Drive EN1 high to enable REG1 or drive EN1 low to disable REG1. EN1 has hysteresis so that an RC may be used to implement manual sequencing with respect to other inputs. In systems based on Marvell PXA3xx processors, EN1, EN2, and EN5 are typically connected to SYS_EN (Table 2). The REG1 step-down regulator operates in either normal or forced-PWM mode. See the REG1-REG4 StepDown DC-DC Converter Operating Modes section for more information. REG1 has an on-chip synchronous rectifier. See the REG1-REG4 Synchronous Rectification section for more information. The REG1 regulator allows 100% duty-cycle operation. See the REG1/REG2 100% Duty-Cycle Operation (Dropout) section for more information.
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Table 3. SET1 Logic
SET1* IN UNCONNECTED GROUND MAX8660/ MAX8660B: V1 (V) 3.3 3.0 2.85 MAX8660A: V1 (V) 2.5 2.0 1.8
*SET1 is latched after REG1 startup.
Table 4. SET2 Logic
SET2* IN UNCONNECTED GROUND MAX8660/MAX8660B/ MAX8661: V2 (V) 3.3 2.5 1.8 MAX8660A: V2 (V) 2.5 2.0 1.8
*SET2 is latched after REG2 startup.
REG2 (VCC_IO, VCC_MEM) Step-Down DC-DC Converters REG2 is a high-efficiency (REG2 + REG8 IQ = 40A) 2MHz current-mode step-down DC-DC converter that outputs up to 900mA with efficiency up to 96%. The output voltage is selected with the SET2 input as shown in Table 4. The REG2 output voltage selection is latched at the end of the REG2 soft-start period. Changes in SET2 after the startup period have no effect.
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
EN2 is a dedicated enable input for REG2. Drive EN2 high to enable REG2 or drive EN2 low to disable REG2. EN2 has hysteresis so that an RC may be used to implement manual sequencing with respect to other inputs. In systems based on Marvell PXA3xx, EN1, EN2, and EN5 are typically connected to SYS_EN (Table 2). The REG2 step-down regulator operates in either normal or forced-PWM mode. See the REG1-REG4 StepDown DC-DC Converter Operating Modes section for more information. The REG2 regulator has an on-chip synchronous rectifier. See the REG1-REG4 Synchronous Rectification section for more information. The REG2 regulator allows 100% duty-cycle operation. See the REG1/REG2 100% Duty-Cycle Operation (Dropout) section for more information. The REG4 step-down regulator operates in either normal or forced-PWM mode. See the REG1-REG4 StepDown DC-DC Converter Operating Modes section for more information. The REG4 regulator has an on-chip synchronous rectifier. See the REG1-REG4 Synchronous Rectification section for more information.
MAX8660/MAX8660A/MAX8660B/MAX8661
REG3 (VCC_APPS) Step-Down DC-DC Converters REG3 is a high-efficiency (REG3 + REG8 IQ = 45A) 2MHz current-mode step-down converter that has an I2C-adjustable output voltage from 0.725V to 1.800V in 25mV increments with efficiency up to 92%. The default REG3 output voltage is 1.4V for the MAX8660/ MAX8660A/MAX8661, and 1.15V for the MAX8660B (contact factory for other default voltages). REG3 delivers up to 1.6A. See the I2C Interface section for details on how to adjust the output voltage. REG3 has an I2C enable bit (EN3) and a shared hardware enable pin (EN34). See the REG3/REG4 Enable (EN34, EN3, EN4) section for more information. The REG3 step-down regulator operates in either normal or forced-PWM mode. See the REG1-REG4 StepDown DC-DC Converter Operating Modes section for more information. The REG3 regulator has an on-chip synchronous rectifier. See the REG1-REG4 Synchronous Rectification section for more information. REG4 (VCC_SRAM) Step-Down DC-DC Converters REG4 is a high-efficiency (REG4 + REG8 IQ = 45A) 2MHz current-mode step-down converter that has an I2C-adjustable output voltage from 0.725V to 1.800V in 25mV increments with efficiency up to 92%. The default REG4 output voltage is 1.4V for the MAX8660/ MAX8660A/MAX8661, and 1.15V for the MAX8660B (contact factory for other default voltages). REG4 delivers up to 400mA. See the I 2C Interface section for details on how to adjust the output voltage. REG4 has an I2C enable bit (EN4) and a shared hardware enable pin (EN34). See the REG3/REG4 Enable (EN34, EN3, EN4) section for more information.
REG1-REG4 Step-Down DC-DC Converter Operating Modes REG1-REG4 independently operate in one of two modes: normal or forced PWM. At power-up or after a reset, REG1-REG4 default to normal operation. Activate forced-PWM mode by setting bits in the FPWM register (Table 9) with the I2C interface. The FPWM bits can be changed at any time. In forced-PWM mode, a converter operates with a constant 2MHz switching frequency regardless of output load. The MAX8660/MAX8661 regulate the output voltage by modulating the switching duty cycle. ForcedPWM mode is ideal for low-noise systems because output voltage ripple is small (< 10mVP-P) and switching harmonics occur at multiples of the constantswitching frequency and are easily filtered. However, light-load power consumption in forced-PWM mode is higher than that of normal mode (Table 7). Normal operation offers improved efficiency at light loads by switching only as necessary to supply the load. With moderate to heavy loading, the regulator switches at a fixed 2MHz switching frequency as it does in forced-PWM mode. This transition to fixed-frequency switching occurs at the load current specified in the following equation:
V - VOUT VOUT IOUT IN x 2xL VIN x fSW
REG1-REG4 Synchronous Rectification Internal n-channel synchronous rectifiers eliminate the need for external Schottky diodes and improve efficiency. The synchronous rectifier turns on during the second half of each switching cycle (off-time). During this time, the voltage across the inductor is reversed, and the inductor current ramps down. In PWM mode, the synchronous rectifier turns off at the end of the switching cycle. In normal mode, the synchronous rectifier turns off when the inductor current falls below 25mA or at the end of the switching cycle, whichever occurs first. REG1/REG2 100% Duty-Cycle Operation (Dropout) The REG1 and REG2 step-down DC-DC converters operate with 100% duty cycle when the supply voltage approaches the output voltage. This allows these
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
converters to maintain regulation until the input voltage falls below the desired output voltage plus the dropout voltage specification of the converter. During 100% duty-cycle operation, the high-side p-channel MOSFET turns on constantly, connecting the input to the output through the inductor. The dropout voltage (VDO) is calculated as follows: VDO = ILOAD (RP + RL) where: RP = p-channel power switch RDS(ON) RL = external inductor ESR The REG1 dropout voltage is 200mV with a 1200mA load (with inductor resistance = 50m). The REG2 dropout voltage is 225mV with a 900mA load (with inductor resistance = 67m).
REG8 (VCC_BBATT) Always-On Regulator The output of REG8 (V8) is always active when the input voltage (VIN) is above the undervoltage-lockout threshold of 2.55V (max) and below the overvoltage-lockout threshold of 6.0V (min). The REG8 linear regulator is supplied from IN and its output regulates to 3.3V and supplies up to 30mA. The internal REG8 pass element is 12 in dropout, providing a 180mV dropout voltage with a 15mA output current. Connect V8 to VCC_BBATT for applications that use Marvell PXA3xx processors. The RSO output goes low if V8 is less than 2.2V (falling typ).
Ramp-Rate Control (RAMP)
REG1 and REG2 have a fixed soft-start ramp that eliminates input current spikes when they are enabled; 200s after being enabled, REG1 and REG2 linearly ramp from 0V to the set output voltage in 450s. When these regulators are disabled, the output voltage decays at a rate determined by the output capacitance, internal 650 discharge resistance, and the external load. The REG3 and REG4 output voltage have a variable linear ramp rate that is set by a resistor connected from RAMP to AGND (RRAMP). This resistor controls the output-voltage ramp rate during soft-start and a positive voltage change (i.e., 1.0V to 1.4V). The negative voltage change (i.e., 1.4V to 1.0V) is controlled in forcedPWM mode, and when the ARD bit is set in normal mode (Table 9). Figure 4 shows the relationship
RAMP RATES vs. RAMP-RATE RESISTOR
12 10 RAMP RATE (mV/s) 8 6 REG3/4/5 DCRR 4 2 0 10 100 RRAMP (k) 1000
Linear Regulators (REG5-REG8)
REG5 (VCC_MVT, VCC_BG, VCC_OSC13M, VCC_PLL) REG5 is a linear regulator with an I2C-adjustable output voltage from 1.700V to 2.000V in 25mV increments (REG5 + REG8 IQ = 55A). The default REG5 voltage is 1.8V. REG5 delivers up to 200mA. See the I2C Interface section for details on how to adjust the output voltage. The power input for the REG5 linear regulator is IN5. The IN5 input voltage range extends down to 2.35V. Note that in the Marvell PXA3xx specification, VCC_MVT is enabled by SYS_EN (along with V1 and V2), but must not rise after V1 (VCC_IO) or V2 (VCC_MEM). This requirement dictates that IN5 be connected to IN and not V1 or V2. EN5 is a dedicated enable input for REG5. Drive EN5 high to enable REG5. Drive EN5 low to disable REG5. EN5 has hysteresis so that an RC may be used to implement manual sequencing with respect to other inputs. In systems with Marvell PXA3xx processors, EN1, EN2, and EN5 are typically connected to SYS_EN (Table 2). REG6/REG7 (VCC_CARD1, VCC_CARD2) The REG6/REG7 linear regulators supply up to 500mA each (REG6 or REG 7 + REG8 IQ = 85A). The output voltages, V6 and V7, are programmable through the serial interface from 1.8V to 3.3V in 0.1V steps (Table 13). See the I2C Interface section for details on changing the V6 or V7 voltage. On the MAX8660, the combined power input for the REG6 and REG7 linear regulators is IN67. On the MAX8661, IN6 is the power input for REG6 (REG7 is not available on the MAX8661). REG6 and REG7 are disabled by default and must be enabled using the I2C serial interface. REG6 and REG7 have independent enable bits in the OVER2 register: EN6 and EN7 (Table 9). To enable the regulators, set the corresponding enable bit.
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REG3/4 SSRR TO: 1V 1.4V 1.8V
1.4 x VOUT [V] mV SSRR = s 0.0014848 x (2.2 x (RAMP [k] + 13.5) + 9) REG / REG4 / REG5 DYNAMIC - CHANGE RAMP RATE (DCRR) : mV 12500 DCRR = s 8 x (2.2 x (RRAMP [k] + 13.5) + 9)
REG3 / REG4 SOFT - START RAMP RATE (SSRR) :
Figure 4. Soft-Start and Voltage-Change Ramp Rates
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
between RRAMP and the output-voltage ramp rates. A 56k R RAMP satisfies the typical requirements of Marvell PXA3xx processors; 200s after being enabled, REG3 and REG4 linearly ramp from 0V to the set output voltage at the rate set by R RAMP . When REG3 and REG4 are disabled, the output voltage decays at a rate determined by the output capacitance, internal 550 discharge resistance, and the external load. Active ramp-down functionality is inherent in forcedPWM operation. In normal-mode operation, active ramp down is enabled by setting ARD3 and ARD4 (Table 9). With "active ramp-down" enabled, the regulator output voltage ramps down at the rate set by RRAMP. With small loads, the regulator must sink current from the output capacitor to actively ramp down the output voltage. In normal mode, with "active ramp-down" disabled, the regulator output voltage ramps down at the rate determined by the output capacitance and the external load; small loads result in an output-voltage decay that is slower than that specified by RRAMP, large loads (> COUT x RAMPRATE) result in an output-voltage decay that is no faster than that specified by RRAMP. 80s after being enabled, REG5 linearly ramps from 0V to the set output voltage in 225s. The ramp rate during a positive voltage change (i.e., 1.8V to 1.9V) is set with RRAMP. During a negative voltage change (i.e., 1.9V to 1.8V), the REG5 output voltage decays at a rate determined by the output capacitance and the external load; however, ramp-down is no faster than the rate specified by RRAMP. When REG5 is disabled, the output voltage decays at a rate determined by the output capacitance, internal 2k discharge resistance, and the external load. 60s after being enabled by I2C, REG6 and REG7 linearly ramp from 0V to the set output voltage in 450s. REG6 and REG7 do not have positive voltage-change (i.e., 1.8V to 2.5V) ramp-rate control. During a positive voltage change, the output-voltage dV/dt is as fast as possible. To avoid this fast output dV/dt, disable REG6 or REG7 before changing the output. With this method, the soft-start ramp rate limits the output dV/dt, and therefore, the input current is controlled. During a negative voltage change (i.e., 2.5V to 1.8V), the REG6 or REG7 output voltage decays at a rate determined by the output capacitance and the external load. When REG6 or REG7 is disabled, the output voltage decays at a rate determined by the output capacitance, internal 350 discharge resistance, and the external load.
Power Sequencing
Enable Signals (EN_, PWR_EN, SYS_EN, I 2C) As shown in Table 5, the MAX8660/MAX8661 feature numerous enable signals for flexibility in many applications. In a typical application with the Marvell PXA3xx processor, many of these enable signals are connected together. EN1, EN2, and EN5 typically connect to the SYS_EN output. With this connection, REG5 is the first supply to rise (if IN5 is connected to IN). EN34 typically connects to Marvell's PWR_EN output. Alternatively, REG3 and REG4 can be activated by the I2C interface (see the REG3/REG4 Enable (EN34, EN3, EN4) section for more information). REG6 and REG7 are activated by the serial interface. REG8 has no enable input and always remains on as long the MAX8660/MAX8661 are powered between the UVLO and OVLO range. All regulators are forced off during UVLO and OVLO. See the Undervoltage and Overvoltage Lockout section for more information. Note: The logic that controls the Marvell PXA3xx processor SYS_EN and PWR_EN signals is powered from the VCC_BBATT power domain.
Table 5. Enable Signals
POWER DOMAIN V1 (VCC_IO) (MAX8660/MAX8660A only) V2 (VCC_MEM) V5 (VCC_MVT) V3 (VCC_APPS) V4 (VCC_SRAM) V6 (VCC_CARD1) V7 (VCC_CARD2) (MAX8660/MAX8660A only) V8 (VCC_BBATT) MAXIM ENABLE SIGNAL HARDWARE EN1 EN2 EN5 EN34 -- -- SOFTWARE -- -- -- EN3 (OVER1) EN4 (OVER1) EN6 (OVER2) EN7 (OVER2) Always on PWR_EN & PWR_I2C Standard I2C -- SYS_EN APPLICATIONS PROCESSOR ENABLE SIGNAL
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
REG3/REG4 Enable (EN34, EN3, EN4) REG3 and REG4 have independent I 2C enable bits (EN3, EN4) and a shared hardware-enable input (EN34). As shown in Figure 5, the EN34 hardwareenable input is logically ORed with the I2C enable bits. Table 6 is the truth table for the V3/V4 enable logic. Note that to achieve a pure I2C enable/disable, connect EN34 to ground. Similarly, to achieve a pure hardware enable/disable, leave the I2C enable bits at their default value (EN3 = EN4 = 0 = off); V3 and V4 cannot be independently enabled/disabled using only hardware. Note: A low MR drives RSO low and returns the I2C registers to their default values: EN3 = 0 and EN4 = 0. Power Modes The MAX8660/MAX8661 provide numerous enable signals (Table 5) and support any combination for enabling and disabling their supplies with these signals. Table 7 shows several power modes defined for PXA3xx processors along with their corresponding MAX8660/ MAX8661 quiescent operating currents. Power-Up and Power-Down Timing Figure 6 shows the power-up sequence for the Marvell PXA3xx family of processors. In general, the supplies should power up in the following order: 1) POWER-UP: V8 V5 V1 and V2 V3 and V4 2) REG6 and REG7 typically power external card slots and can be powered up and down based on application requirements. Note that the Marvell PXA3xx processor controls EN1/EN2/EN5 with the same SYS_EN signal, yet Marvell's timing diagrams show that V5 is supposed to power up before V1 and V2. Because of the PXA3xx family's timing parameters, most systems connect EN1/EN2/EN5 together and drive them with SYS_EN. When powering up, this connection ensures that V5 powers up before V1 and V2 (only when V5 is powered from IN). Marvell PXA3xx Power Configuration Register (PCFR) The MAX8660/MAX8661 comply with the Marvell PXA3xx power I2C register specifications. This allows the PMIC to be used along with the processor with littleto-no software development. As shown in Table 9, there are many I2C registers, but since the processor automatically updates the PMIC through its power I2C interface, only the REG6 and REG7 enable bits need be programmed to fully utilize the PMIC. The Marvell PXA3xx processor contains a power management unit general configuration register (PCFR). The default values of this register are compliant with the MAX8660/MAX8661. However, wake-up performance can be optimized using this register: * The PCFR register contains timers for the SYS_DEL and PWR_DEL timing parameters as shown in Figure 6. Each timer defaults to 125ms. When using the MAX8660/MAX8661, these timers may be shortened to 2ms to speed up the overall system wake-up delay. * Enabling the "shorten wake-up delay" function (SWDD bit) bypasses the SYS_DEL and PWR_DEL timers and uses voltage detectors on the Marvell PXA3xx processor to optimize the overall system wake-up delay.
PV3
BATT
LX3 REG3 EN34 PG3
V3 (VCC_APPS)
ON SDA SCL EN3 I2C EN4 ON LX4 REG4 PG4 V4 (VCC_SRAM) PV4 BATT
Figure 5. V3/V4 Enable Logic
Table 6. Truth Table for V3/V4 Enable Logic
HARDWARE INPUT EN34 0 0 0 X 1 X = Don't care. EN3 0 (default) 0 1 1 X I2C BITS EN4 0 (default) 1 0 1 X V3 OFF OFF ON ON ON V4 OFF ON OFF ON ON
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Table 7. Power Modes and Corresponding Quiescent Operating Currents
POWER MODE ALL ON POWER DOMAIN STATE DIGITAL CONTROL STATE MAX8660 QUIESCENT OPERATING CURRENT (FIGURE 3) NORMAL FORCED-PWM OPERATING MODE MODE 250A 23mA
V1, V2, V3, V4, V5, V6, V7, EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN) and V8 are on are asserted. V6, V7 are enabled by I2C V1, V2, V3, V4, V5, EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN) RUN, IDLE, and V8 are on are asserted and STANDBY V6 and V7 are off V6 and V7 are disabled by I2C (default) V1, V2, V5, and V8 are on SLEEP DEEP SLEEP EN1/EN2/EN5 (SYS_EN) are asserted EN34 (PWR_EN) is deasserted; V6 and V7 V3, V4, V6, and V7 are off are disabled by I2C (default) EN1/EN2/EN5 (SYS_EN) and EN34 (PWR_EN) All supplies off except V8 are deasserted; V6, V7 are disabled by I2C
140A
22.9mA
90A
10mA
20A
Note: Forced-PWM currents are measured on the MAX8660 EV kit. Currents vary with step-down inductor and output capacitor tolerance.
V8 (VCC_BBATT) tVBHRSTH = 20ms, MIN (TIMED BY PMIC) RSO (nRESET) tVBHBFH = 0s, MIN (TIMED BY PMIC) LBO (nBATT_FAULT) EN1/EN2/EN5 (SYS_EN) tSEHVMH = SYS_DEL TIME, MAX (TIMED BY PMIC) V5 (VCC_MVT) tVMHVSH1 = SYS_DEL TIME, tSEHVMH, MAX (TIMED BY PMIC) V1 (VCC_IO) tVMHVSH2 = SYS_DEL TIME - t, tSEHVMH, MAX (TIMED BY PMIC) V2 (VCC_MEM) tSEHPH = SYS_DEL TIME + 152s, MIN tSEHPH = SYS_DEL TIME + 153s, MAX (TIMED BY MARVELL PXA3xx) tBFHSEH = 93.75s, MAX (TIMED BY MARVELL PXA3xx) tBSTHSEH = 2.05s, MAX (TIMED BY MARVELL PXA3xx)
EN34 (PWR_EN) SCL FROM AP (PWR_SCL) SCA FROM AP (PWR_SDA) nRESET_OUT* FROM AP V3 (VCC_APPS) V4 (VCC_SRAM)
tSHROH = SYS_DEL TIME +213s, MIN tSHROH = SYS_DEL TIME +214s, MAX (TIMED BY MARVELL PXA3xx) tPHLVTH3 = PWR_DEL TIME (TIMED BY PMIC)
tPHLVTH4 = PWR_DEL TIME (TIMED BY PMIC)
*THE MAX8660/MAX8661 DO NOT DIRECTLY USE THE MARVELL PXA3xx PROCESSOR'S nRESET_OUT LOGIC OUTPUT.
Figure 6. Power-Up Timing
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Voltage Monitors, Reset, and Undervoltage-Lockout Functions
Undervoltage and Overvoltage Lockout When the V IN is below V UVLO (typically 2.35V), the MAX8660/MAX8661 enter its undervoltage-lockout mode (UVLO). UVLO forces the device to a dormant state. In UVLO, the input current is very low (1.5A) and all regulators are off. RSO and LBO are forced low when the input voltage is between 1V (typ) and VUVLO. The I2C does not function in UVLO, and the I2C register contents are reset in UVLO.
When the input voltage is above VOVLO (typically 6.35V) the MAX8660/MAX8661 enter overvoltage-lockout mode (OVLO). OVLO mode protects the MAX8660/ MAX8661 from high-voltage stress. In OVLO, the input current is 25A and all regulators are off. RSO is held low, the I2C does not function, and register contents are reset in OVLO. LBO continues to function in OVLO; however, since LBO is typically pulled up to V8 (VCC_BBATT), LBO appears to go low in OVLO because V8 is disabled. Alternatively, LBO may be pulled up to IN. LBR and LBF monitor the input voltage (usually a battery) and trigger the LBO output (Figure 7). The truth table in Figure 7 shows that LBO is high impedance when the voltage from LBR to AGND (VLBR) exceeds the low-battery rising threshold (VLBRTH = 1.25V (typ). LBO is low when the voltage from LBF to AGND (VLBF) falls below the low-battery falling threshold (VLBFTH = 1.20V typ). On power-up, the LBR threshold must be exceeded before LBO deasserts. Connecting LBF to LBR and to a two-resistor voltagedivider sets a 50mV hysteresis referred to LBF (hysteresis at the battery voltage is scaled up by the resistor value), connecting LBF and LBR separately to a threeresistor voltage-divider (Figure 7) allows the falling threshold and rising threshold to be set separately (achieving larger hysteresis). The Figure 7 resistor values are selected as a function of the desired falling (VLBOF) and rising (VLBOR) thresholds as follows: First, select R3 in the 100k to 1M range: VLBOR V x 1 - LBFTH VLBRTH VLBOF V x VLBOR R2 = R 3 x LBFTH - 1 VLBRTH x VLBOF R1 = R 3 x
Reset Output (RSO) and MR Input RSO is an open-drain reset output. As shown in Figure 1, RSO typically connects to the nRESET input of the applications processor and is pulled up to V8 (VCC_BBATT). A low on nRESET causes the processor to enter its reset state. RSO is forced low when one or more of the following conditions occur: * MR is low. * V8 is below VRSOTH (2.2V falling typ). * VIN is below VUVLO (2.35V typ). * VIN is above VOVLO (6.35V typ). RSO is high impedance when all of the following conditions are satisfied: * MR is high. * V8 is above VRSOTH (2.35V rising typ). * VUVLO < VIN < VOVLO. * The RSO deassert delay (tVBHRSTH = 24ms typ) has expired. When RSO goes low, the MAX8660/MAX8661 I2C registers are reset to their default values. If the MR feature is not required, connect MR high. If the RSO feature is not required, connect RSO low. Low-Battery Detector (LBO, LBF, LBR) LBO is an open-drain output that typically connects to the nBATT_FAULT input of the applications processor to indicate that the battery has been removed or discharged (Figure 1). LBO is typically pulled up to V8 (VCC_BBATT).
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V8 (VCC_BBATT) + R1 LBF S Q AGND R2 VLBFTH 1.200V LBR R R3 VLBRTH 1.250V IN
MAX8660 MAX8661
LBO
TRUTH TABLE LBF VLBF < VLBFTH VLBF < VLBFTH VLBF > VLBFTH VLBF > VLBFTH LBR VLBR < VLBRTH VLBR > VLBRTH VLBR < VLBRTH VLBR > VLBRTH LBO 0 0 HOLD 1
Figure 7. Low-Battery Detector Functional Diagram
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
where VLBOR is the rising voltage at the top of R1 (typically VIN) when LBO goes high, and VLBOF is the falling voltage at the top of R1 when LBO goes low. For example, to set VLBOR to 3.6V and VLBOF to 3.2V, choose R3 to be 1M. Then, R1 = 1.8M and R2 = 80k. If the low-battery-detector feature is not required, connect LBO to ground and connect LBF and LBR to IN.
I2C Interface
An 2-wire serial interface controls a variety of MAX8660/MAX8661 functions: * The output voltages of V3-V7 are set by the serial interface. * Each of the four step-down DC-DC converters (REG1-REG4) can be put into forced-PWM operation. * REG3 and REG4 can be enabled by the serial interface or by a hardware-enable pin (EN34). See the REG3/REG4 Enable (EN34, EN3, EN4) section for more information. * REG6 and REG7 are activated only by the serial interface. The serial interface operates whenever VIN is between VUVLO (typically 2.40V) and VOVLO (typically 6.35V). When VIN is outside the I2C operation range, the I2C registers are reset to their default values. The serial interface consists of a bidirectional serial-data line (SDA) and a serial-clock input (SCL). The MAX8660/ MAX8661 are slave-only devices, relying upon a master to generate a clock signal. The master (typically the applications processor) initiates data transfer on the bus and generates SCL to permit data transfer. I2C is an open-drain bus. SDA and SCL require pullup resistors (500 or greater). Optional resistors (24) in series with SDA and SCL protect the device inputs from high-voltage spikes on the bus lines. Series resistors also minimize cross-talk and undershoot on bus signals. The Marvell PXA3xx specification contains an extensive list of registers for various functions, not all of which are provided on the MAX8660/MAX8661. The list in Table 9 is a subset of the Marvell list as it relates to functions included in the PMIC. Even though the MAX8660/MAX8661 use a subset of the specified registers, they acknowledge writes to the entire register space (0x00 to 0xFF). In Marvell PXA3xx applications, the pullups are typically to VCC_IOx. I2C-compatible,
MAX8660/MAX8660A/MAX8660B/MAX8661 MAX8660/MAX8660A/MAX8660B/MAX8661
Internal Off-Discharge Resistors
Each regulator on the MAX8660/MAX8661 has an internal resistor that discharges the output capacitor when the regulator is off (Table 8). The internal discharge resistors pull their respective output to ground when the regulator is off, ensuring that load circuitry always powers down completely. The internal off-discharge resistors are active when a regulator is disabled, when the device is in OVLO, and when the device is in UVLO with VIN greater than 1.0V. With VIN less than 1.0V, the internal off-discharge resistors may not activate.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in the MAX8660/MAX8661. When internal thermal sensors detect a die temperature in excess of +160C, the corresponding regulator(s) are shut down, allowing the IC to cool. The regulators turn on again after the junction cools by 15C, resulting in a pulsed output during continuous thermal-overload conditions. A thermal overload on any of REG1 through REG5 only shuts down the overloaded regulator. An overload on REG6 or REG7 shuts down both regulators together. During thermal overload, REG8 is not turned off, and the I2C interface and voltage monitors remain active.
Table 8. Internal Off-Discharge Resistor
REGULATOR REG1 REG2 REG3 REG4 REG5 REG6 REG7 REG8 INTERNAL OFF-DISCHARGE RESISTOR VALUE 650 30% 650 30% 550 30% 550 30% 2k 30% 350 30% 350 30% 1.5k 30%
Data Transfer One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section for more information).
Each transmit sequence is framed by a START (S) condition and a STOP (P) condition. Each data packet is 9 bits long; 8 bits of data followed by the acknowledge bit. The MAX8660/MAX8661 suport data transfer rates with SCL frequencies up to 400kHz.
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MAX8660/MAX8660A/MAX8660B/MAX8661
DATA BIT FUNCTION 7 R Default R EN7** 0 R AVS 0 0 AGO 0 0 0 EN6 Default MVS Default R Default R Default R Default R Default R Default R Default 0 0 0 R R 0 0 0 0 0 R R 0 0 0 1 1 R R 0 0 0 1 1 R R 0 0 0 1 1 0 R R 0 0 0 1 1 0 1 R R 0 0 0 0 0 MGO SVS SGO R 0 0 0 0 0 -- -- -- -- -- 0 0 0 0 0 0 0 0 R R R R EN4 (S_EN) R EN3 (A_EN) 6 5 4 3 2 1 0
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
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Output-Voltage Enable Register 1. Enables/disables V3 and V4. See the REG3/REG4 Enable (EN34, EN3, EN4) section for more information. Output-Voltage Enable Register 2. Enables/disables V6 and V7. See the REG6/REG7 (VCC_CARD1, VCC_CARD2) section for more information. Voltage-Change Control Register. Independently specifies that the V3, V4, and V5 output voltage must follow either target register 1 or 2. See Table 10. V3 (VCC_APPS) Target 1--See Table 11 1 VCC_APPS (V3) DVM Target Voltage 1 Register. Sets target 1 voltage for V3. V3 (VCC_APPS) Target 2--See Table 11 1 1 VCC_APPS (V3) DVM Target Voltage 2 Register. Sets target 2 voltage for V3. V4 (VCC_SRAM) Target 1--See Table 11 0 1 1 VCC_SRAM (V4) DVM Target Voltage 1 Register. Sets target 1 voltage for V4. V4 (VCC_SRAM) Target 2--See Table 11 0 1 V5 (VCC_MVT) Target 1--See Table 12 0 1 0 V5 (VCC_MVT) Target 2--See Table 12 0 1 0 V6 Voltage--See Table 13 0 0 0 0 0 0 0 0 1 VCC_SRAM (V4) DVM Target Voltage 2 Register. Sets target 2 voltage for V4. VCC_MVT (V5) Target Voltage 1 Register. Sets target 1 voltage for V5. VCC_MVT (V5) DVM Target Voltage 2 Register. Sets target 2 voltage for V5. V7 Voltage--See Table 13 Default 0 0 LDO1 and LDO2 Voltage-Control Register (V6 and V7 on MAX8660). Specifies the V6 and V7 output voltage. V6 and V7 are enabled/disabled with OVER2. ARD4 ARD3 -- -- FPWM4 FPWM3 FPWM2 FPWM1** Forced-PWM Register. The FPWM_ bits allow V1, V2, V3, and V4 to independently operate in either skip mode or forcedPWM mode. See the REG1-REG4 Step-Down DC-DC Converter Operating Modes section for more information. The ARD_ bits allow the output voltage to be actively ramped down during negative voltage transitions See the Ramp-Rate Control (RAMP) section for more information. Note that this is a Maxim custom register that is not required by the Marvell PXA3xx processor. Default 0 0 0 0 0 0 0 0
Table 9. I2C Registers
REGISTER ADDRESS
REGISTER NAME
R/W
0x10
OVER1*
W
0x12
OVER2
W
0x20
VCC1*
W
0x23
ADTV1*
W
0x24
ADTV2*
W
0x29
SDTV1*
W
0x2A
SDTV2*
W
0x32
MDTV1
W
0x33
MDTV2
W
0x39
L12VCR
W
0x80
FPWM
W
R means these data locations are designated reserved in the Marvell PXA3xx specification.
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Note: The MAX8660/MAX8661 acknowledge attempts to write to the entire address space from 0x00 to 0xFF, even though only a subset of those addresses actually exist in the IC.
* These registers are accessed by the power I2C bus of the Marvell PXA3xx processor.
** Maintain these bits at their default 0 value for the MAX8661.
High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
S SDA tSU;STA SCL tHD;STA tHD;STA tSU;STO Sr P
Figure 8. START and STOP Conditions
START and STOP Conditions When the serial interface is inactive, SDA and SCL idle high. A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA, while SCL is high (Figure 7).
A START condition from the master signals the beginning of a transmission to the MAX8660/MAX8661. The master terminates transmission by issuing a notacknowledge followed by a STOP condition (see the Acknowledge Bit section for more information). The STOP condition frees the bus. To issue a series of commands to the slave, the master may issue repeated start (Sr) commands instead of a stop command in order to maintain control of the bus. In general, a repeated start command is functionally equivalent to a regular start command. When a STOP condition or incorrect address is detected, the MAX8660/MAX8661 internally disconnect SCL from the serial interface until the next START condition, minimizing digital noise and feedthrough.
S SDA
Acknowledge Bit Both the master and the MAX8660/MAX8661 (slave) generate acknowledge bits when receiving data. The acknowledge bit is the last bit of each 9-bit data packet. To generate an acknowledge (A), the receiving device must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse (Figure 9). To generate a not acknowledge (A), the receiving device allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse and leaves it high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. Slave Address A bus master initiates communication with a slave device (MAX8660/MAX8661) by issuing a START condition followed by the slave address. As shown in Figure 10, the slave address byte consists of 7 address bits and a read/write bit (R/W). After receiving the proper address, the MAX8660/MAX8661 issue an acknowledge by pulling SDA low during the ninth clock cycle. Note that the R/W bit is always zero since the MAX8660/ MAX8661 are write only.
The Marvell PXA3xx processor supports 0x68 (SRAD = GND) as the I2C slave address.
NOT ACKNOWLEDGE ACKNOWLEDGE
MAX8660/MAX8660A/MAX8660B/MAX8661
tSU:DAT SCL 1 2 8 9
tHD:DAT
Figure 9. Acknowledge Bits
SRAD 0 (GND) 1 (IN) 0 1 1 SLAVE ADDRESS (WRITE) BINARY 0b 0110 1000 0b 0110 1010 0 HEXADECIMAL 0x68 0x6A 1 0 R/W=0 (WRITE ONLY) SRAD 0 ACKNOWLEDGE
S SDA
A
SCL
1
2
3
4
5
6
7
8
9
Figure 10. Slave Address Byte
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Table 10. DVM Voltage-Change Register (VCC1, 0x20)
REGISTER ADDRESS REGISTER NAME BIT NAME FUNCTION V5 (VCC_MVT) voltage select: 0--Ramp V5 to voltage selected by MDTV1 (default) 1--Ramp V5 to voltage selected by MDTV2 Start V5 (VCC_MVT) voltage change: 0--Hold V5 at current level (default) 1--Ramp V5 as selected by MVS V4 (VCC_SRAM) voltage select: 0--Ramp V4 to voltage selected by SDTV1 (default) 1--Ramp V4 to voltage selected by SDTV2 Start V4 (VCC_SRAM) voltage change: 0--Hold V4 at current level (default) 1--Ramp V4 as selected by SVS Reserved Reserved V3 (VCC_APPS) voltage select: 0--Ramp V3 to voltage selected by ADTV1 (default) 1--Ramp V3 to voltage selected by ADTV2 Start V3 (VCC_APPS) voltage change: 0--Hold V3 at current level (default) 1--Ramp V3 as selected by AVS
7
MVS
6
MGO
5
SVS
0x20
VCC1
4 3 2 1
SGO R R AVS
0
AGO
I 2C Write Operation The MAX8660/MAX8661 are write-only devices and recognize the "write byte" protocol as defined in the SMBus specification and shown in section A of Figure 11. The "write byte" protocol allows the I 2C master device to send 1 byte of data to the slave device. The "write byte" protocol requires a register pointer address for the subsequent write. The MAX8660/MAX8661 acknowledge any register pointer even though only a subset of those registers actually exists in the device. The "write byte" protocol is as follows: 1) The master sends a start command.
2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends an 8-bit register pointer. 5) The slave acknowledges the register pointer. 6) The master sends a data byte. 7) The slave updates with the new data. 8) The slave acknowledges the data byte. 9) The master sends a STOP condition.
In addition to the write-byte protocol, the MAX8660/ MAX8661 recognize the multiple byte register-data pair protocol as shown in section B of Figure 11. This protocol allows the I2C master device to address the slave only once and then send data to multiple registers in a random order. Registers may be written continuously until the master issues a STOP condition. The multiple-byte register-data pair protocol is as follows: 1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit. 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends an 8-bit register pointer. 5) The slave acknowledges the register pointer. The master sends a data byte. The slave updates with the new data. The slave acknowledges the data byte. Steps 5 to 7 are repeated as many times as the master requires. Registers may be accessed in random order. 10)The master sends a STOP condition. 6) 7) 8) 9)
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Table 11. Serial Codes for V3 (VCC_APPS) and V4 (VCC_SRAM) Output Voltages
REGISTER ADDRESS REGISTER NAME DATA BYTE OUTPUT VOLTAGE (V)* 0x00 0.725 0x01 0.750 0x02 0.775 0x03 0.800 0x04 0.825 0x05 0.850 0x06 0.875 0x07 0.900 0x08 0.925 0x09 0.950 0x0A 0.975 0x0B 1.000 0x0C 1.025 0x0D 1.050 0x0E 1.075 0x0F 1.100 0x10 1.125 0x11 1.150** 0x12 1.175 0x13 1.200 0x14 1.225 0x23 ADTV1 0x15 1.250 0x24 ADTV2 0x29 SDTV1 0x16 1.275 0x2A SDTV2 0x17 1.300 0x18 1.325 0x19 1.350 0x1A 1.375 0x1B 1.400 (default)*** 0x1C 1.425 0x1D 1.450 0x1E 1.475 0x1F 1.500 0x20 1.525 0x21 1.550 0x22 1.575 0x23 1.600 0x24 1.625 0x25 1.650 0x26 1.675 0x27 1.700 0x28 1.725 0x29 1.750 0x2A 1.775 0x2B 1.800 *Contact factory for other default voltages. **MAX8660B default voltage is 1.15V. ***MAX8660/MAX8660A/MAX8661 default voltage is1.4V.
Table 12. Serial Codes for V5 Output Voltage
REGISTER ADDRESS REGISTER NAME DATA BYTE 0x00 0x01 0x02 0x03 0x04 0x32 0x33 MDTV1 MDTV2 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C OUTPUT VOLTAGE (V) 1.700 1.725 1.750 1.775 1.800 (default) 1.825 1.850 1.875 1.900 1.925 1.950 1.975 2.000
MAX8660/MAX8660A/MAX8660B/MAX8661
Table 13. Serial Codes for V6 and V7 Output Voltages
REGISTER ADDRESS REGISTER NAME DATA NIBBLE 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF OUTPUT VOLTAGE (V) 1.8 (default) 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3
0x39
L12VCR
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
LEGEND MASTER TO SLAVE SLAVE TO MASTER
A. WRITING TO A SINGLE REGISTER WITH THE "WRITE BYTE" PROTOCOL 1 S 7 SLAVE ADDRESS R/W B. WRITING TO MULTIPLE REGISTERS WITH THE "MULTIPLE-BYTE REGISTER-DATA PAIR" PROTOCOL 1 S 7 SLAVE ADDRESS R/W 8 REGISTER POINTER n 1 A 8 DATA n 1 A NUMBER OF BITS 1 0 1 A 8 REGISTER POINTER X 1 A 8 DATA X 1 A NUMBER OF BITS 1 0 1 A 8 REGISTER POINTER 1 A 8 DATA 1 1 NUMBER OF BITS
AP
8 REGISTER POINTER Z
1 A
8 DATA Z
1
1
NUMBER OF BITS
AP
Figure 11. Writing to the MAX8660/MAX8661
Design Procedure
Setting the Output Voltages
The REG1 and REG2 regulators each have three preset voltages that are programmed with the SET1 and SET2 inputs. See the REG1 (VCC_IO) Step-Down DC-DC Converter and REG2 (VCC_IO, VCC_MEM) Step-Down DC-DC Converters sections for more information. V8 is fixed at 3.3V and cannot be changed. V3-V7 are set by the I 2 C interface. See the I 2 C Interface section for more information. Note that while operating in forced-PWM mode with an input voltage greater than 4.3V, the minimum output voltage of REG3 and REG4 is limited by the minimum duty cycle. In forced-PWM mode, the minimum output voltage for REG3 or REG4 is: V3MIN = 0.167 x VPV3 V4 MIN = 0.167 x VPV4 Note that the above minimum voltage limitation does not apply to normal-mode operation.
Inductor Selection
Calculate the inductor value (LIDEAL) for each of REG1 through REG4 as follows: LIDEAL = 4 x VIN x D x (1 - D) IOUT(MAX) x fOSC
This sets the peak-to-peak inductor current ripple to 1/4 the maximum output current. The oscillator frequency, fOSC, is 2MHz, and the duty cycle, D, is: V D = OUT VIN Given LIDEAL, the peak-to-peak inductor ripple current is 0.25 x IOUT(MAX). The peak inductor current is 1.125 x IOUT(MAX). Make sure that the saturation current of the inductor exceeds the peak inductor current, and the rated maximum DC inductor current exceeds the maximum output current (I OUT(MAX)). Inductance values smaller than LIDEAL can be used to reduce inductor size; however, if much smaller values are used, peak inductor current rises and a larger output capacitance may be required to suppress output ripple. Larger
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
inductance values than LIDEAL can be used to obtain higher output current, but typically require physically larger inductor size. Refer to the MAX8660 EV kit data sheet for specific inductor recommendations. Additional ripple due to capacitor ESR is: VRIPPLE(ESR) = IL(PEAK) x ESR Refer to the MAX8660 EV kit data sheet for specific output capacitor recommendations.
MAX8660/MAX8660A/MAX8660B/MAX8661
Input Capacitor Selection
The input capacitor in a step-down DC-DC converter reduces current peaks drawn from the battery or other input power source and reduces switching noise in the controller. The impedance of the input capacitor at the switching frequency should be less than that of the input source so that high-frequency switching currents do not pass through the input source. The input capacitor must meet the input-ripple-current requirement imposed by the step-down converter. Ceramic capacitors are preferred due to their resilience to power-up surge currents. Choose the input capacitor so that the temperature rise due to input ripple current does not exceed approximately 10C. For a step-down DC-DC converter, the maximum input ripple current is 1/2 of the output. This maximum input ripple current occurs when the step-down converter operates at 50% duty factor (VIN = 2 x VOUT). Refer to the MAX8660 EV kit data sheet for specific input capacitor recommendations.
Applications Information
Power Dissipation
The MAX8660/MAX8661 have a thermal-shutdown feature that protects the IC from damage when the die temperature exceeds +160C (see the Thermal-Overload Protection section for more information). To prevent thermal overload and allow the maximum load current on each regulator, it is important to ensure that the heat generated by the MAX8660/MAX8661 can be dissipated into the PC board. The exposed pad must be soldered to the PC board, with multiple vias under the exposed pad (EP) conducting heat to a ground plane. The junction-to-case thermal resistance (JC) of the MAX8660/MAX8661 is 2.7C/W. When properly mounted on a multilayer PC board, the junction-to-ambient thermal resistance (JA) is typically 28C/W.
PCB Layout and Routing
Good printed circuit board (PCB) layout is necessary to achieve optimal performance. Conductors carrying discontinuous currents and any high-current path must be made as short and wide as possible. Refer to the MAX8660 EV kit data sheet for an example of a good PCB layout. Place the bypass capacitors for each power input pair (IN to AGND, PV1 to PG1, PV2 to PG2, PV3, to PG3, and PV4 to PG4) as close as possible to the IC. The exposed pad (EP) is the main path for heat to exit the IC. Connect EP to the ground plane with multiple vias to allow heat to dissipate from the device.
Output Capacitor Selection
The step-down DC-DC converter output capacitor keeps output ripple small and ensures control-loop stability. The output capacitor must also have low impedance at the switching frequency. Ceramic, polymer, and tantalum capacitors are suitable, with ceramic exhibiting the lowest ESR and lowest high-frequency impedance. Output ripple due to capacitance (neglecting ESR) is approximately: IL(PEAK ) VRIPPLE = 2 x fOSC x COUT
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Package Marking
TOP VIEW
Ordering Information (continued)
PART PIN-PACKAGE OPTIONS V1: 2.5V, 2.0V, 1.8V V2: 2.5V, 2.0V, 1.8V V3: 1.4V (default) V4: 1.4V (default) V1: 3.3V, 3.0V, 2.85V V2: 3.3V, 2.5V, 1.8V V3: 1.15V (default) V4: 1.15V (default) No REG1 and REG7 V2: 3.3V, 2.5V, 1.8V V3: 1.4V (default) V4: 1.4V (default)
8660E TLyww + aaaa
8660AE TLyww + aaaa
8661E TLyww + aaaa
MAX8660AETL+
40 Thin QFN
MAX8660BETL+
40 Thin QFN
"yww" is a date code. "aaaa" is an assembly code.
+Denotes lead-free packaging and marks pin 1 location.
MAX8661ETL+ 40 Thin QFN
Note: All devices are specified over the -40C to 85C operating temperature range. +Denotes lead(Pb)-free/RoHS-compliant package.
Chip Information
PROCESS: BiCMOS
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN PACKAGE CODE T4055-1 DOCUMENT NO. 21-0140
MAX8660/MAX8660A/MAX8660B/MAX8661
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QFN THIN.EPS
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications MAX8660/MAX8660A/MAX8660B/MAX8661
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
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High-Efficiency, Low-IQ, PMICs with Dynamic Voltage Management for Mobile Applications
Revision History
REVISION NUMBER 2 REVISION DATE 8/09 DESCRIPTION Added MAX8660B and automotive part options, and replaced Intel references with Marvell PAGES CHANGED 1, 2, 3, 5, 6, 7, 10, 11, 19-34, 36, 37
MAX8660/MAX8660A/MAX8660B/MAX8661
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 43
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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